This survey describes research directions in netlist partitioning during the past two decades
in terms of both problem formulations and solution approaches. We discuss the traditional …

Logic locking refers to a set of techniques that can protect integrated circuits (ICs) from
counterfeiting, piracy and malicious functionality changes by an untrusted foundry. It …

Many algorithms for congestion control, scheduling, network measurement, active queue
management, and traffic engineering require custom processing of packets in the data plane …

We describe the capabilities of and algorithms used in a new FPGA CAD tool, Versatile
Place and Route (VPR). In terms of minimizing routing area, VPR outperforms all published …

Since their introduction in 1984, Field-Programmable Gate Arrays (FPGAs) have become
one of the most popular implementation media for digital circuits and have grown into a $2 …

Reconfigurable Computing marks a revolutionary and hot topic that bridges the gap
between the separate worlds of hardware and software design—the key feature of …

This paper presents a technique for preprocessing combinational logic before technology
mapping. The technique is based on the representation of combinational logic using And …

We use a fully timing-driven experimental flow [4][15] in which a set of benchmark circuits
are synthesized into different cluster-based [2][3][15] logic block architectures, which contain …

The VPR toolset has been widely used in FPGA architecture and CAD research, but has not
evolved over the past decade. This article describes and illustrates the use of a new version …

In this papel; we investigate the speed and area-eficiency of FPGAs employing “logic
clusters” containing multiple LUTs and registers as their logic block. We introduce a new …