An integrated circuit for data encryption/decryption and secure key management is
disclosed. The integrated circuit may be used in conjunction with other integrated circuits …

An encryption technique is disclosed for encrypting a data segment comprising a plurality of
data blocks, wherein the security and throughput of the encryption is enhanced by using …

A re-configurable logic device such as a field programmable gate array (FPGA) can be used
to deploy a data processing pipeline, the pipeline comprising a plurality of pipelined data …

A re-configurable logic device such as a field programmable gate array (FPGA) can be used
to deploy a data processing pipeline, the pipeline comprising a plurality of pipelined data …

Methods and apparatuses for processing data are disclosed, including methods and
apparatuses that leverage a reconfigurable logic device to offload decompression and …

An encryption technique is disclosed for encrypting a plurality of data blocks of a data
segment where the encryption selectively switches between a blockwise independent …

(57) ABSTRACT A re-configurable logic device Such as a field programmable gate array
(FPGA) can be used to deploy a data processing pipeline, the pipeline comprising a plurality …

6.023760 A 2/2000 Karttunen 7,167,980 B2 1/2007 Chiu 6,028,939 A 2, 2000 Yin 7,181,437
B2 2/2007 Indeck et al. 6,044,375 A 3, 2000 Shmueli et al. 7,181,608 B2 2/2007 Fallon et al …

Methods and systems are disclosed where a plurality of precompiled hardware templates
are stored in memory, each of the hardware templates being configured for loading onto a re …

(57) ABSTRACT A hardware cryptographic engine implementing an Advanced Encryption
Standard (AES) algorithm is dis closed. The hardware cryptographic engine comprises a …