Analog to digital converters (ADC): A literature review
The signal processing is advancing day by day as its needs and in wireline/wireless
communication technology from 2G to 4G cellular communication technology with CMOS …
communication technology from 2G to 4G cellular communication technology with CMOS …
A 3bit/cycle 1GS/s 8-bit SAR ADC Employing Asynchronous Ping-Pong Quantization Scheme
Y Guo, X Liu, J Jin, J Zhou - 2022 IEEE International …, 2022 - ieeexplore.ieee.org
This paper presents a 3bit/cycle 1GS/s8-bit SAR ADC with asynchronous ping-pong
quantization scheme. With the proposed scheme, settling requirement of the reference …
quantization scheme. With the proposed scheme, settling requirement of the reference …
Energy efficient comparator-less current-mode TFET-CMOS co-integrated scalable flash ADC
N Gupta, H Shrimali, A Makosiej… - … on Circuits and …, 2021 - ieeexplore.ieee.org
This paper presents a novel TFET-CMOS co-integrated comparator-less, energy-efficient
ADC architecture. The design utilizes the Negative Differential Resistance property of TFETs …
ADC architecture. The design utilizes the Negative Differential Resistance property of TFETs …
A 6-bit Low-Area Hybrid ADC Design For System-on-Chip Measurements
N Kolahimahmoudi, G Insinga, S Roggi… - … on Design, Test and …, 2024 - ieeexplore.ieee.org
In recent years, with the declining dimensions of transistors, the system-on-chips (SoCs)
have had more physical defects. These physical defects ultimately result in failures that …
have had more physical defects. These physical defects ultimately result in failures that …
[PDF][PDF] DESIGN OF A COMPARATOR AND AN AM-PLIFIER IN CMOS USING STANDARD LOGIC GATES
TMR CARAPINHA - 2023 - run.unl.pt
Design Of A Comparator And An Amplifier In CMOS Using Standard Logic Gates.
Copyright©< Tiago R. Carapinha>, NOVA School of Science and Technology, NOVA …
Copyright©< Tiago R. Carapinha>, NOVA School of Science and Technology, NOVA …
A 8-b 1GS/s 2b/cycle SAR ADC in 28-nm CMOS
This paper presents a high-speed 2b/cycle SAR ADC. By resolving their comparison time
with a 1-bit TDC, the number of comparators are reduced to two instead of three in a …
with a 1-bit TDC, the number of comparators are reduced to two instead of three in a …
An Efficient Technique for Pipelined SAR ADC with Dynamic Bulk Biasing Design
Pipelined ADCs are becoming increasingly prevalent in SOC design, both as standalone
parts and integrated functional units. The ADC employs a novel method that includes sub …
parts and integrated functional units. The ADC employs a novel method that includes sub …