We present a unique 32-bit binary-to-binary logarithm converter including its CMOS VLSI
implementation. The converter is implemented using combinational logic only and it …

Addition is the key operation in digital systems, and floating-point adder (FPA) is frequently
used for real number addition because floating-point representation provides a large …

Design of the leading zero anticipator (LZA) or detector (LZD) is pivotal to the normalization
of results for addition and fused multiplication-addition in high-performance floating point …

A logical statement has a value that is either true or false, t or f for short. Such statements can
be combined in logical expressions by logical operators. In this treatise the logical operators …

This paper describes the design of a leading-one prediction (LOP) logic for floating-point
addition with an exact determination of the shift amount for normalization of the adder result …

Most commercial and academic floating point libraries for FPGAs (field programmable gate
arrays) provide only a small fraction of all possible floating point units. In contrast, the …

A pipelined single-precision floating-point multiply-accumulator (FPMAC) featuring a single-
cycle accumulate loop using base 32 and internal carry-save arithmetic with delayed …

The book is designed to serve as a textbook for courses offered to undergraduate and
graduate students enrolled in electrical, electronics, and communication engineering. The …

In this paper, a new leading-zero counter (or detector) is presented. New boolean relations
for the bits of the leading-zero count are derived that allow their computation to be performed …

Performance of field-programmable gate arrays (FPGAs) used for floating-point applications
is poor due to the complexity of floating-point arithmetic. Implementing floating-point units …