Selective replication of data structures
GA Bouchard, DA Carlson, RE Kessler - US Patent 7,558,925, 2009 - Google Patents
Related US Application Data(74) Attorney, Agent, or Firm—Hamilton, Brook, Smith & (63)
Continuation-in-part of application No. 1 1/221,365, Reynolds, PC filed on Sep. 7, 2005, now …
Continuation-in-part of application No. 1 1/221,365, Reynolds, PC filed on Sep. 7, 2005, now …
Direct access to low-latency memory
GA Bouchard, DA Carlson, RE Kessler… - US Patent …, 2009 - Google Patents
A content aware application processing system is provided for allowing directed access to
data stored in a non-cache memory thereby bypassing cache coherent memory. The …
data stored in a non-cache memory thereby bypassing cache coherent memory. The …
Resizable and relocatable memory scratch pad as a cache slice
MA Mohamed, H Park - US Patent 5,966,734, 1999 - Google Patents
A cache system supports a re-sizable software-managed fast scratch pad that is
implemented as a cache-slice. A processor register indicates the size and base address of …
implemented as a cache-slice. A processor register indicates the size and base address of …
Na channels, disease, and related assays and compositions
ML Brown, S Grindrod, TH Walls, T Hansen… - US Patent …, 2014 - Google Patents
2009-09-29 Assigned to GEORGETOWN UNIVERSITY reassignment GEORGETOWN
UNIVERSITY ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …
UNIVERSITY ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR …
Methods and compositions related to clot binding compounds
E Ruoslahti, D Simberg - US Patent 9,101,671, 2015 - Google Patents
US9101671B2 - Methods and compositions related to clot binding compounds - Google Patents
US9101671B2 - Methods and compositions related to clot binding compounds - Google Patents …
US9101671B2 - Methods and compositions related to clot binding compounds - Google Patents …
Local scratchpad and data caching system
DH Asher, DA Carlson, RE Kessler - US Patent 7,941,585, 2011 - Google Patents
A RISC-type processor includes a main register file and a data cache. The data cache can
be partitioned to include a local memory, the size of which can be dynamically changed on a …
be partitioned to include a local memory, the size of which can be dynamically changed on a …
Method and apparatus for managing write back cache
D Asher, G Bouchard, R Kessler… - US Patent App. 11 …, 2006 - Google Patents
(57) ABSTRACT A network Services processor includes an input/output bridge that avoids
unnecessary updates to memory when cache blockS Storing processed packet data are no …
unnecessary updates to memory when cache blockS Storing processed packet data are no …
Parallel DSP demodulation for wideband software-defined radios
OS Haddadin, BT Hansen, DS Nelson… - US Patent …, 2010 - Google Patents
US7697641B2 - Parallel DSP demodulation for wideband software-defined radios - Google
Patents US7697641B2 - Parallel DSP demodulation for wideband software-defined radios …
Patents US7697641B2 - Parallel DSP demodulation for wideband software-defined radios …
Global processor resource assignment in an assembler
JF Garvey, CD Jeffries - US Patent 7,111,287, 2006 - Google Patents
An assembler for assembling code is disclosed. The assem bly language code includes a
plurality of code blocks associated with resource-needs, such as variables, and resources …
plurality of code blocks associated with resource-needs, such as variables, and resources …
A combinatorial architecture for instruction-level parallelism
E Berkovich, S Berkovich - Microprocessors and Microsystems, 1998 - Elsevier
The work presents a new principle for microprocessor design based on a pairwise-balanced
combinatorial arrangement of processing and memory elements. The proposed apparatus …
combinatorial arrangement of processing and memory elements. The proposed apparatus …