FinFET basic cells evaluation for regular layouts

C Meinhardt, R Reis - … IEEE 4th Latin American Symposium on …, 2013 - ieeexplore.ieee.org
This work evaluates the use of finFET to design a set of basic blocks targeting a regular
layout. The main advantage of this approach is a reduction on area and power consumption …

Standard cell like via-configurable logic blocks for structured ASIC in an industrial design flow

HH Tung, RB Lin, MC Li… - IEEE transactions on very …, 2011 - ieeexplore.ieee.org
A structured application-specific integrated circuit (ASIC) has prefabricated yet configurable
logic block arrays. We investigate some important via-configurable logic block (VCLB) …

Comparing high-performance cells in CMOS bulk and FinFET technologies

C Meinhardt, R Reis - … IEEE 5th Latin American Symposium on …, 2014 - ieeexplore.ieee.org
Technology evolution brings new challenges to integrated circuits (IC) design. Parameter
variation and complex design rules demand a great effort to create suitable design …

A yield-driven regular layout synthesis

C Meinhardt, R Reis - 2013 IEEE Computer Society Annual …, 2013 - ieeexplore.ieee.org
The continuous devices shrinking has introduced new challenges to integrated circuit
design, mainly to deal with the overall yield loss (Beckett 2002). Designers start to take into …

A regular fabric design methodology for applications requiring specific layout-level design rules

S Dupuis, L Noury, N Fel - Microelectronics Journal, 2014 - Elsevier
Regular fabrics have been introduced as an approach to bridge the gap between ASICs and
FPGAs in terms of cost and performance. Indeed, compared to an ASIC, by predefining most …

HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning

Y Shin, I Shin, D Baek, D Kim… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
A structured ASIC, one kind of programmable logic device (PLD), consists of a
homogeneous array of programmable logic elements, or called tiles. The architecture of …

Introducing irregularity to routing architecture of structured ASIC for better routability

I Shin, D Baek, Y Shin - 2012 International Conference on Field …, 2012 - ieeexplore.ieee.org
Imposing regularity presents a fundamental limitation to any structured ASIC, or more
generally any programmable logic device. It has been recently shown that irregularity can be …

[引用][C] 이종구조를갖는Programmable Logic 의Routability 를개선하기위한패킹알고리즘

신인섭, 김덕환, 신영수 - 대한전자공학회학술대회, 2011 - dbpia.co.kr
Heterogenous array of programmable logic (HAPL) can overcome the limitation of
conventional programmable logic by using more than one type of tile. However, it suffers …