Nanophotonic is a promising solution for on-chip interconnection due to its intrinsic low-
latency and low-power features. Future tiled chip multiprocessors (CMPs) for rich client …

Future many-core CMP designs that will integrate tens of processor cores on-chip will be
constrained by area and power. Area constraints make impractical the use of a bus or a …

This paper proposes DCC (Dynamic Cache Clustering), a novel distributed cache
management scheme for large-scale chip multiprocessors. Using DCC, a per-core cache …

Nanophotonic interconnection is a promising solution for inter-core communication in future
chip multiprocessors (CMPs). Main benefits derive from its intrinsic low-latency and high …

This paper presents CMP-VR (Chip-Multiprocessor with Victim Retention), an approach to
improve cache performance by reducing the number of off-chip memory accesses. The …

Multi-core architectures have emerged as the best alternative to take advantage of the
increasing number of transistors currently offered in a single die. For example, the dual-core …

Although directory-based cache-coherence protocols are the best choice when designing
chip multiprocessors with tens of cores on-chip, the memory overhead introduced by the …

Power consumption in current high-performance chip multiprocessors (CMPs) has become
a major design concern that aggravates with the current trend of increasing the core count. A …

The non-uniform distribution of memory accesses among the cache sets results in some sets
being used heavily while certain others remaining underutilized. Dynamic associativity …

As the core counts increase in each chip multiprocessor generation, coherence protocols
should improve scalability inperformance, area, and energy consumption to meet the …