Chebyshev stopbands for CIC decimation filters and CIC-implemented array tapers in 1D and 2D

JO Coleman - IEEE Transactions on Circuits and Systems I …, 2012 - ieeexplore.ieee.org
The stopbands of a cascaded integrator-comb (CIC) decimation filter are ordinarily very
narrow, as each results from a single multiple zero. Here response sharpening with a …

[HTML][HTML] Incorporation of reduced full adder and half adder into wallace multiplier and improved carry-save adder for digital FIR filter

S Chinnapparaj, D Somasundareswari - Circuits and Systems, 2016 - scirp.org
Improvement of digital FIR filter is vital in the field of Digital Signal Processing in order to
reduce the area, delay and power. Multiplication and Accumulation (MAC) unit of Finite …

Implementation of FIR Filter Using Wallace Reduction Tree For High Speed Application

MVP Amudalapalli, NM Leena… - 2024 First …, 2024 - ieeexplore.ieee.org
The increasing demand for high-speed digital signal processing has necessitated the
development of efficient FIR filter architectures. Conventional multipliers, such as Baugh …

Low Complexity Techniques for Low Density Parity Check Code Decoders and Parallel Sigma-Delta ADC Structures

A Blad - 2011 - diva-portal.org
In this thesis, contributions are made in the area of receivers for wireless communication
standards. The thesis consists of two parts, focusing on implementations of forward error …

Low-complexity parallel evaluation of powers exploiting bit-level redundancy

M Abbas, O Gustafsson, A Blad - 2010 Conference Record of …, 2010 - ieeexplore.ieee.org
In this work, we investigate the problem of computing any requested set of power terms in
parallel using summations trees. This problem occurs in applications like polynomial …

[引用][C] Electronics Systems

O Gustafsson - 2011 - Linköpings universitet