Residue number systems: A new paradigm to datapath optimization for low-power and high-performance digital signal processing applications
CH Chang, AS Molahosseini… - IEEE circuits and …, 2015 - ieeexplore.ieee.org
Residue Number System (RNS) is a non-weighted number system which was proposed by
Garner back in 1959 to achieve fast implementation of addition, subtraction and …
Garner back in 1959 to achieve fast implementation of addition, subtraction and …
IPP@ HDL: Efficient intellectual property protection scheme for IP cores
In this paper, a procedure for intellectual property protection (IPP) of digital circuits called
IPP@ HDL is presented. Its aim is to protect the author rights in the development and …
IPP@ HDL is presented. Its aim is to protect the author rights in the development and …
On modulo 2^ n+ 1 adder design
HT Vergos, G Dimitrakopoulos - IEEE transactions on …, 2010 - ieeexplore.ieee.org
Two architectures for modulo 2 n+ 1 adders are introduced in this paper. The first one is built
around a sparse carry computation unit that computes only some of the carries of the modulo …
around a sparse carry computation unit that computes only some of the carries of the modulo …
Design and implementation of an RNS-based 2-D DWT processor
Y Liu, EMK Lai - IEEE Transactions on Consumer Electronics, 2004 - ieeexplore.ieee.org
Discrete wavelet transform has been incorporated as part of the JPEG2000 image
compression standard and is used in many consumer imaging products. This paper …
compression standard and is used in many consumer imaging products. This paper …
Encryption Using Residue Number System: Research Trends and Future Challenges
R Shevchuk, I Yakymenko… - 2024 14th International …, 2024 - ieeexplore.ieee.org
This paper presents a comprehensive knowledge mapping and in-depth analysis of the
application of residue number system in encryption technique research to understand better …
application of residue number system in encryption technique research to understand better …
Optimized implementation of RNS FIR filters based on FPGAs
In this paper optimized Residue Number System (RNS) arithmetic blocks to better exploit
some of the architectural characteristics of the last generation FPGAs are presented. The …
some of the architectural characteristics of the last generation FPGAs are presented. The …
Fast Modulo 2^{n}-(2^{n-2}+ 1) Addition: A New Class of Adder for RNS
RA Patel, M Benaissa… - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
Efficient modular adder architectures are invaluable to the design of residue number system
(RNS)-based digital systems. For example, they are used to perform residue encoding and …
(RNS)-based digital systems. For example, they are used to perform residue encoding and …
An optimized two-level discrete wavelet implementation using residue number system
HY Alzaq, BB Ustundag - EURASIP Journal on Advances in Signal …, 2018 - Springer
Using discrete wavelet transform (DWT) in high-speed signal processing applications
imposes a high degree of caution to hardware resource availability, latency and power …
imposes a high degree of caution to hardware resource availability, latency and power …
Power-performance enhancement of two-dimensional RNS-based DWT image processor using static voltage scaling
Digital image processing is widely used in fast and high-performance applications. The high
speed and functional requirements of such applications, however, lead to increased power …
speed and functional requirements of such applications, however, lead to increased power …
A comparative performance of discrete wavelet transform implementations using multiplierless
H Alzaq, BB Üstündağ - Wavelet theory and its applications, 2018 - books.google.com
Using discrete wavelet transform (DWT) in high-speed signal-processing applications
imposes a high degree of care to hardware resource availability, latency, and power …
imposes a high degree of care to hardware resource availability, latency, and power …