This paper presents an overview of common-centroid (CC) layout styles, used in analog
designs to overcome the impact of systematic variations. CC layouts must be carefully …

This article presents an automatic layout generation framework in advanced CMOS
technologies. The framework extends the template-and-grid-based layout generation …

Process variations and the effect of interconnect parasitics can cause significant
perturbations in the performance metrics of capacitive digital-to-analog converters (DACs) …

The layout area and power consumption of a charge-scaling digital-to-analog converter
(DAC) is typically dominated by the capacitor array. For a binary-weighted DAC, since the …

The layout area and power consumption of a binary-weighted capacitive digital-to-analog
converter (DAC) increases exponentially with the number of bits. To meet linearity targets …

In analog circuits, process variation can cause unpredictability in circuit performance.
Common-centroid (CC) type layouts have been shown to mitigate process-induced …

The design of active array structures in analog circuits requires careful matching to minimize
the impact of variations. This work presents a constructive approach for building these arrays …

Building upon recent advances in analog electronic design automation (EDA), this paper
discusses directions for reinforcing the connection between design and EDA, in order to …

The ALIGN (Analog Layout, Intelligently Generated from Netlists) project [1, 2] is a joint
university-industry effort to push the envelope of automated analog layout through a …

Arrays of active and passive devices are widely employed to translate large transistor sizes
from a circuit schematic to their layout implementation. For example, capacitive digital-to …