This paper presents a novel method for full-chip statistical leakage estimation that considers
the impact of process variation. The proposed method considers the correlations among …

This paper focuses on statistical optimization and, more specifically, timing yield (TY)-
constrained optimization. For cell replacement in timing-constrained optimization, we need …

As CMOS devices become smaller, process variations‐induced uncertainty imposes a large
spread in the circuit timing and therefore, it becomes one of the main issues for circuit yield …

The increasing process variations which goes along with the continuing CMOS technology
shrinking necessitate accurate statistical timing analysis. Multiple Input Simultaneous …

In this paper we investigate the impact of intra-and inter-die variations on the delay
sensitivity of certain Residue Number System (RNS) arithmetic circuits in comparison to …

With the significant advancement of statistical timing and yield analysis algorithms, there is a
strong need for accurate and analytical spatial correlation models. In this paper, we propose …

Incremental analysis is indispensible for efficient circuit optimization, as it analyzes the effect
by the modified circuit part only instead of analyzing a whole circuit again from beginning …

While first-order statistical static timing analysis (SSTA) techniques enjoy good runtime
efficiency desired for tackling large industrial designs, more accurate second-order SSTA …

持續縮小元件大小的互補式金氧半導體製程技術造成了在晶片上的高功率密度.
這個事實導致在超大型積體電路上有很高的晶片溫度. 晶片溫度將會影響到電路效能以及可靠度 …

The most recent research of SSTA requires accurate non-Gaussian data processing
modeling. Although quadratic Gaussian forms have been proposed to data modeling …