A proposed design and FPGA implementation of a demodulator and phase compensation
system is presented. The system is simple, accurate, dissipate low power. Simulations …

A fast-locking all-digital phase-locked loop (ADPLL) including a fast-locking unit, a multi-
level bang-bang phase detector (ML-BBPD), a dynamic gain adjustment controller (DGAC) …

As the HPC community moves into the exascale computing era, application energy is
becoming as large of a concern as performance. Optimizing for energy will be essential in …

This paper presents a novel technique to reduce the locking time in Digital Phase-Locked
Loop (DPLL) based on Bang-Bang Phase Detector (BB-PD). The implemented 65-nm …

This presents an all-digital phase-locked loop (ADPLL) system using triple-stage phase-
shifting (TSPS) for fast locking. At the first stage, a phase-pulling multiplexer linearly pulls the …

The enhancement in the settling response of frequency synthesizers would open up
prospects for new applications such as spread spectra and frequency hopping systems …

Due to the nonlinear behavior caused by the charge pump, charge pump phase-locked
loops (CPPLLs) are nonlinear systems. In an ideal charge pump, the applied current is …

In phase locked loops, settling time and tuning range form important performance
parameters, in addition to jitter and power consumption. However, most PLLs are designed …

We propose a multi-phase Direct Digital Synthesizer (DDS) based Digital to Time Converter
(DTC), for application in fractional-N Digital Phase Locked Loops (DPLLs). The proposed …

We propose a Digial-to-Time Converter (DTC) that is capable of providing infinite-delay-over-
time for application in low-jitter digital phase locked loops. The DTC is implemented using …