Hardware vulnerabilities are generally considered more difficult to fix than software ones
because they are persistent after fabrication. Thus, it is crucial to assess the security and fix …

Due to shrinking technology, increasing functional frequency and density, and reduced
noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise …

Faster-than-at-speed test have been proposed to detect small delay defects. While these
techniques increase the test frequency to reduce the positive slack of the path, they …

The sensitivity of very deep submicron designs to supply voltage noise is increasing due to
higher path delay variations and reduced noise margins with supply noise scaling. The …

The increasing gap between modern chip frequencies and test clock frequencies provided
by external test equipment, makes at-speed delay testing a challenge. We present a novel …

Interconnect defects such as weak resistive opens, shorts, and bridges increase the path
delay affected by a pattern during manufacturing test but are not significant enough to cause …

The BurstModetrade test clocking methodology, first presented in, is improved to handle
circuits with synchronous clocks of different frequencies. An on-chip clock controller allows …

Most scan based designs implement the scan enable as a slow speed global control signal,
and can therefore only implement launch-on-capture (LOC) delay tests. Launch-onshift …

Small delay defect (SDD) and aging-induced circuit failure are both prominent reliability
concerns for nanoscale integrated circuits. Faster-than-at-speed testing is effective on SDD …

The Delay Test Scan Flip-Flop (DTSFF) has been recently presented as a low cost DFT
technique to achieve both launch-on-shift (LOS) and launch-on-capture (LOC) scan delay …