Large scale distributed visualization on computational Grids: A review

L Wang, D Chen, Z Deng, F Huang - Computers & Electrical Engineering, 2011 - Elsevier
Advances in science and engineering have put high demands on tools for high performance
large-scale data exploration and analysis. Visualization is a powerful technology for …

Reconstruction and evolution of 3D model on asphalt pavement surface texture using digital image processing technology and accelerated pavement testing

XP Ji, S Zhu, Y Sun, H Li, Y Chen… - Road Materials and …, 2023 - Taylor & Francis
Asphalt pavement surface texture is the main factor affecting pavement function.
Reconstruction of the asphalt pavement surface texture is needed to accurately reveal its …

The design revolution of logarithmic number system architecture

SZM Naziri, RC Ismail… - 2014 2nd International …, 2014 - ieeexplore.ieee.org
Logarithmic number system (LNS) has been a trend in digital signal processing (DSP) for
recent years, particularly digital image processing. LNS was been implemented in DSP …

Novel binary divider architecture for high speed VLSI applications

R Senapati, BK Bhoi, M Pradhan - 2013 IEEE Conference on …, 2013 - ieeexplore.ieee.org
Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique
computational technique for calculations based on 16 Sutras (Formulae). Novel Binary …

Practical recognition system for text printed on clear reflected material

K Mohammad, S Agaian - International Scholarly Research …, 2012 - Wiley Online Library
Text embedded in an image contains useful information for applications in the medical,
industrial, commercial, and research fields. While many systems have been designed to …

FPGA‐based implementation of floating point processing element for the design of efficient FIR filters

TM John, S Chacko - IET Computers & Digital Techniques, 2021 - Wiley Online Library
Numerous applications based on very large scale intergration (VLSI) architecture suffer from
large size components that lead to an error in the design of the filter during the stages of …

Design and evaluation of high-performance processing elements for reconfigurable systems

SS Purohit, SR Chalamalasetti… - IEEE transactions on …, 2012 - ieeexplore.ieee.org
In this paper, we present the design and evaluation of two new processing elements for
reconfigurable computing. We also present a circuit-level implementation of the data paths …

[HTML][HTML] A hybrid level set model for image segmentation

W Chen, C Liu, A Basu, B Pan - Plos one, 2021 - journals.plos.org
Active contour models driven by local binary fitting energy can segment images with
inhomogeneous intensity, while being prone to falling into a local minima. However, the …

Extended depth of field in images through complex amplitude pre-processing and optimized digital post-processing

LM Ledesma-Carrillo, M Lopez-Ramirez… - Computers & Electrical …, 2014 - Elsevier
Many applications require images with high resolution and an extended depth of field.
Directly changing the depth of field in optical systems results in losing resolution and …

VLSI implementation of high speed area efficient arithmetic unit using vedic mathematics

V KN - ICTACT Journal on Microelectronics, 2016 - article.publish4promo.com
High speed Arithmetic Units (AUs) are widely used in architectures used in signal and image
processing applications. AUs involve multi-functions and have multiplier as the critical …