Coupling processors with acceleration hardware is an effective manner to improve energy
efficiency of embedded systems. Many-core is nowadays a dominating design paradigm for …

Multiple constraints in SPMs are considered a problem that can be solved in a
nondeterministic polynomial time. In this paper, we propose a novel approach solving the …

Distribution system state estimation (DSSE) and distribution system power flow (DSPF) are
two applications provided by the distribution management (DMS) system that are constantly …

Efficient caching of the data block in the buffer cache can overcome, the costly delays,
associated with accesses made to secondary storage devices. Pattern based buffer cache …

In real-time memory-intensive image processing and vision applications, increasing image
resolution requires the use of external SDR/DDR memories. However, the arbitrary pixel …

Heterogeneous multi-core architectures with CPUs and accelerators attract many attentions
since they can achieve power-efficient computing in various areas from low-power …

Replacement algorithms designed for the multi-level cache found in Chip Multi Processors
(CMP), in specific, heterogeneous multi-core processors, might result in data redundancy …

With the rapid development of the computer software and hardware technologies, various
mobile devices have been broadly applied in people's daily life, such as smart phones and …

For an FPGA-based heterogeneous multicore platform, we present the design methodology
to reduce the total processing time considering data-transfer. The reconfigurability of recent …

Heterogeneous multi-core architectures with CPUs and accelerators attract many attentions
since they can achieve power-efficient computing in various areas from low-power …