Extreme ultraviolet lithography and three dimensional integrated circuit—A review

B Wu, A Kumar - Applied Physics Reviews, 2014 - pubs.aip.org
The term 3D IC generally means an IC package having multiple device layers, which is
different with 3D transistor structures such as the FinFET. 3D packaging and 3D integration …

Three-dimensional integrated circuits

AW Topol, DC La Tulipe, L Shi, DJ Frank… - IBM Journal of …, 2006 - ieeexplore.ieee.org
Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active
devices, have the potential to dramatically enhance chip performance, functionality, and …

Photonic multiply-accumulate operations for neural networks

MA Nahmias, TF De Lima, AN Tait… - IEEE Journal of …, 2019 - ieeexplore.ieee.org
It has long been known that photonic communication can alleviate the data movement
bottlenecks that plague conventional microelectronic processors. More recently, there has …

The future of wires

R Ho, KW Mai, MA Horowitz - Proceedings of the IEEE, 2001 - ieeexplore.ieee.org
Concern about the performance of wires wires in scaled technologies has led to research
exploring other communication methods. This paper examines wire and gate delays as …

Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0

N Muralimanohar, R Balasubramonian… - 40th Annual IEEE …, 2007 - ieeexplore.ieee.org
A significant part of future microprocessor real estate will be dedicated to 12 or 13 caches.
These on-chip caches will heavily impact processor performance, power dissipation, and …

[图书][B] Reconfigurable computing: the theory and practice of FPGA-based computation

S Hauck, A DeHon - 2010 - books.google.com
Reconfigurable Computing marks a revolutionary and hot topic that bridges the gap
between the separate worlds of hardware and software design—the key feature of …

An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches

C Kim, D Burger, SW Keckler - … of the 10th international conference on …, 2002 - dl.acm.org
Growing wire delays will force substantive changes in the designs of large caches.
Traditional cache architectures assume that each level in the cache hierarchy has a single …

Dynamic branch prediction with perceptrons

DA Jiménez, C Lin - Proceedings HPCA Seventh International …, 2001 - ieeexplore.ieee.org
This paper presents a new method for branch prediction. The key idea is to use one of the
simplest possible neural networks, the perceptron, as an alternative to the commonly used …

Towards developing high performance RISC-V processors using agile methodology

Y Xu, Z Yu, D Tang, G Chen, L Chen… - 2022 55th IEEE/ACM …, 2022 - ieeexplore.ieee.org
While research has shown that the agile chip design methodology is promising to sustain
the scaling of computing performance in a more efficient way, it is still of limited usage in …

Theory of latency-insensitive design

LP Carloni, KL McMillan… - … on computer-aided …, 2001 - ieeexplore.ieee.org
The theory of latency-insensitive design is presented as the foundation of a new correct-by-
construction methodology to design complex systems by assembling intellectual property …