IBM POWER8 processor core microarchitecture

B Sinharoy, JA Van Norstrand… - IBM Journal of …, 2015 - ieeexplore.ieee.org
The POWER8™ processor is the latest RISC (Reduced Instruction Set Computer)
microprocessor from IBM. It is fabricated using the company's 22-nm Silicon on Insulator …

Optics in computing: From photonic network-on-chip to chip-to-chip interconnects and disintegrated architectures

T Alexoudi, N Terzenidis, S Pitris… - Journal of Lightwave …, 2018 - ieeexplore.ieee.org
Following a decade of radical advances in the areas of integrated photonics and computing
architectures, we discuss the use of optics in the current computing landscape attempting to …

IBM POWER7 multicore server processor

B Sinharoy, R Kalla, WJ Starke, HQ Le… - IBM Journal of …, 2011 - ieeexplore.ieee.org
The IBM POWER® processor is the dominant reduced instruction set computing
microprocessor in the world today, with a rich history of implementation and innovation over …

Last-level cache deduplication

Y Tian, SM Khan, DA Jiménez, GH Loh - Proceedings of the 28th ACM …, 2014 - dl.acm.org
Caches are essential to the performance of modern micro-processors. Much recent work on
last-level caches has focused on exploiting reference locality to improve efficiency …

Architectural enhancements in Stratix V™

D Lewis, D Cashman, M Chan, J Chromczak… - Proceedings of the …, 2013 - dl.acm.org
This paper describes architectural enhancements in the Altera Stratix-V" FPGA architecture,
built on a 28nm TSMC process, together with the data supporting those choices. Among the …

Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules

A Agrawal, A Ansari, J Torrellas - 2014 IEEE 20th International …, 2014 - ieeexplore.ieee.org
EDRAM cells require periodic refresh, which ends up consuming substantial energy for
large last-level caches. In practice, it is well known that different eDRAM cells can exhibit …

III–V-on-Si photonic crystal nanocavity laser technology for optical static random access memories

T Alexoudi, D Fitsios, A Bazin, P Monnier… - IEEE Journal of …, 2016 - ieeexplore.ieee.org
Heterogeneous integration of III-V semiconductors on silicon has gained considerable
momentum fueled by the need to implement fully functional photonic devices and circuits in …

The 12-core power8™ processor with 7.6 tb/s io bandwidth, integrated voltage regulation, and resonant clocking

EJ Fluhr, S Baumgartner, D Boerstler… - IEEE Journal of Solid …, 2014 - ieeexplore.ieee.org
POWER8™ is a 12-core processor fabricated in IBM's 22 nm SOI technology with core and
cache improvements driven by big data applications, providing 2.5× socket performance …

Field tolerant dynamic intrinsic chip ID using 32 nm high-K/metal gate SOI embedded DRAM

S Rosenblatt, D Fainstein, A Cestero… - IEEE journal of solid …, 2013 - ieeexplore.ieee.org
A random intrinsic chip ID generation method using retention fails is implemented in 32 nm
SOI embedded DRAM. A dynamic key algorithm employs a unique pair of 4 Kb binary …

Refrint: Intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies

A Agrawal, P Jain, A Ansari… - 2013 IEEE 19th …, 2013 - ieeexplore.ieee.org
As manycores use dynamic energy ever more efficiently, static power consumption becomes
a major concern. In particular, in a large manycore running at a low voltage, leakage in on …