[HTML][HTML] Performance optimization of high-K pocket hetero-dielectric TFET using improved geometry design
This study explores the optimization of a hetero-dielectric tunnel field-effect transistor
(HDTFET) structure to improve device performance. By incorporating a high-k oxide pocket …
(HDTFET) structure to improve device performance. By incorporating a high-k oxide pocket …
A compact model for nanowire tunneling-FETs
B Lu, D Wang, Y Cui, Z Li, G Chai… - IEEE transactions on …, 2021 - ieeexplore.ieee.org
The nanowire gate-all-around structure with the ultimate channel electrostatic integrity
exhibits the best immunity to short channel effects and improved scaling capability …
exhibits the best immunity to short channel effects and improved scaling capability …
Drain current model for double gate tunnel-FETs with InAs/Si heterojunction and source-pocket architecture
H Lu, B Lu, Y Zhang, Y Zhang, Z Lv - nanomaterials, 2019 - mdpi.com
The practical use of tunnel field-effect transistors is retarded by the low on-state current. In
this paper, the energy-band engineering of InAs/Si heterojunction and novel device structure …
this paper, the energy-band engineering of InAs/Si heterojunction and novel device structure …
An energy-efficient Ge-based leaky integrate and fire neuron: Proposal and analysis
In this paper, we propose an energy-efficient Ge-based Leaky Integrate and Fire (LIF)
neuron and analyze it using a well calibrated 2D simulation model. The proposed neuron …
neuron and analyze it using a well calibrated 2D simulation model. The proposed neuron …
A non-quasi-static model for nanowire gate-all-around tunneling field-effect transistors
B Lu, X Ma, D Wang, G Chai, L Dong… - Chinese Physics B, 2023 - iopscience.iop.org
Nanowires with gate-all-around (GAA) structures are widely considered as the most
promising candidate for 3-nm technology with the best ability of suppressing the short …
promising candidate for 3-nm technology with the best ability of suppressing the short …
A charge-based capacitance model for double-gate hetero-gate-dielectric tunnel FET
In this paper, a charge-based capacitance model has been proposed for a double-gate (DG)
hetero-gate-dielectric tunnel FET (HGD-TFET). By solving the Poisson equation, the surface …
hetero-gate-dielectric tunnel FET (HGD-TFET). By solving the Poisson equation, the surface …
Analysis of non-uniform hetero-gate-dielectric dual-material control gate TFET for suppressing ambipolar nature and improving radio-frequency performance
HF Xu, J Cui, W Sun, XF Han - Chinese Physics B, 2019 - iopscience.iop.org
A tunnel field-effect transistor (TFET) is proposed by combining various advantages
together, such as non-uniform gate–oxide layer, hetero-gate-dielectric (HGD), and dual …
together, such as non-uniform gate–oxide layer, hetero-gate-dielectric (HGD), and dual …
Miller capacitance reduction in negative capacitance TFETs
ABSTRACT A dielectric stacked hetero-gate topology is proposed to reduce the Miller
capacitance in a negative capacitance double gate TFET. An analytical charge-based model …
capacitance in a negative capacitance double gate TFET. An analytical charge-based model …
Compact Capacitance Model of L-Shape Tunnel Field-Effect Transistors for Circuit Simulation.
Although the compact capacitance model of point tunneling types of tunneling field-effect
transistors (TFET) has been proposed, those of line tunneling types of TFETs have not been …
transistors (TFET) has been proposed, those of line tunneling types of TFETs have not been …
Threshold voltage modeling of negative capacitance double gate tfet
An analytical gate threshold voltage model for Negative Capacitance Double Gate Tunnel
Field Effect Transistor (NC-DG TFET) based on the physical definition of threshold voltage in …
Field Effect Transistor (NC-DG TFET) based on the physical definition of threshold voltage in …