Design of hybrid second-level caches

A Valero, J Sahuquillo, S Petit… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
In recent years, embedded dynamic random-access memory (eDRAM) technology has been
implemented in last-level caches due to its low leakage energy consumption and high …

Analyzing the optimal ratio of SRAM banks in hybrid caches

A Valero, J Sahuquillo, S Petit… - 2012 IEEE 30th …, 2012 - ieeexplore.ieee.org
Cache memories have been typically implemented with Static Random Access Memory
(SRAM) technology. This technology presents a fast access time but high energy …

Performance and cache access time of SRAM-eDRAM hybrid caches considering wire delay

YH Gong, HB Jang, SW Chung - International Symposium on …, 2013 - ieeexplore.ieee.org
Most modern microprocessors have multi-level on-chip caches with multi-megabyte shared
last-level cache (LLC). By using multi-level cache hierarchy, the whole size of on-chip …

[PDF][PDF] Prestaciones y consumo de caches hıbridas variando la proporción de bancos SRAM

Las memorias cache se han implementado normalmente con tecnologıa SRAM. Esta
tecnologıa presenta un tiempo de acceso rápido pero consumo de energıa elevado y baja …

Hybrid caches: design and data management

A Valero Bresó - 2013 - riunet.upv.es
Las memorias cache han sido implementadas normalmente con tecnologıa Static Random-
Access Memory (SRAM) ya que es la tecnologıa de memoria electrónica más rápida. Sin …

[PDF][PDF] Hybrid caches: design and data management

AV Bresó - 2013 - researchgate.net
This chapter introduces some concepts and presents the motivation for the work developed
in this thesis. First, different semiconductor memory technologies are discussed, showing …

Analyzing the optimal ratio of SRAM banks in hybrid caches

J Duato, P Lopez, S Petit, A Valero… - 2012 IEEE 30th …, 2012 - computer.org
Cache memories have been typically implemented with Static Random Access Memory
(SRAM) technology. This technology presents a fast access time but high energy …