Max-min fairness has been recognized as an optimal throughput-fairness definition.
However, its realization in packet switching networks and its computational requirements …

This paper proposes a power-aware cache block allocation algorithm for the way-selective
set-associative cache on embedded systems to reduce energy consumption without …

Many-core chip multiprocessor offers high parallel processing power for big data analytics;
however, they require efficient multi-level cache and interconnection to achieve high system …

This paper proposes a modified two-way set associative cache for embedded systems to
reduce the energy consumption. For this goal, the proposed cache, called SSA (selective …

Research on caches has traditionally concentrated on the L1 cache. Most of the
improvements in the design of L2 caches have been rather simple: increase in size and …

Dynamically reconfigurable split cache architecture is a reconfigurable architecture that has
all advantages of a split cache and also the ability to reconfigure itself allowing …

The introduction of embedded processors into field programmable gate arrays (FPGA)
allows the implementation of a new type of systems on chip (SOC) designs which are the …

Multimedia applications are required to process the huge amount of data at high speed in
real time. The memory reference instructions such as loads and stores are the main factor …