Silicon odometers: Compact in situ aging sensors for robust system design
Circuit reliability issues such as bias temperature instability, hot carrier injection, time-
dependent dielectric breakdown, electromigration, and random telegraph noise have …
dependent dielectric breakdown, electromigration, and random telegraph noise have …
NBTI degradation: From transistor to SRAM arrays
V Huard, C Parthasarathy, C Guerin… - 2008 IEEE …, 2008 - ieeexplore.ieee.org
A novel composite model had been recently introduced to physically explain the mean
pMOS threshold voltage shift (V TP) induced by NBTI degradation at transistor level in a …
pMOS threshold voltage shift (V TP) induced by NBTI degradation at transistor level in a …
Effect of BTI degradation on transistor variability in advanced semiconductor technologies
S Pae, J Maiz, C Prasad… - IEEE Transactions on …, 2008 - ieeexplore.ieee.org
The effect of PMOS transistor negative bias temperature instability (NBTI) on product
performance is a key reliability concern. As technology scales and device dimensions …
performance is a key reliability concern. As technology scales and device dimensions …
Universality of NBTI-From devices to circuits and products
S Mahapatra, V Huard, A Kerber… - 2014 IEEE …, 2014 - ieeexplore.ieee.org
This paper showcases the universality of NBTI and its dependencies on time, bias,
temperature, AC frequency and pulse duty cycle across different process integration …
temperature, AC frequency and pulse duty cycle across different process integration …
SRAM-based NBTI/PBTI sensor system design
NBTI has been a major aging mechanism for advanced CMOS technology and PBTI is also
looming as a big concern. This work first proposes a compact on-chip sensor design that …
looming as a big concern. This work first proposes a compact on-chip sensor design that …
Development of a technique for characterizing bias temperature instability-induced device-to-device variation at SRAM-relevant conditions
SRAM is vulnerable to device-to-device variation (DDV), since it uses minimum-sized
devices and requires device matching. In addition to the as-fabricated DDV at time-zero …
devices and requires device matching. In addition to the as-fabricated DDV at time-zero …
SRAM variability and supply voltage scaling challenges
R Kapre, K Shakeri, H Puchner… - 2007 IEEE …, 2007 - ieeexplore.ieee.org
We have developed a methodology for SRAM cell design that unifies all the major design
criterion-cell stability, write margin, read speed and leakage into a single metric. This metric …
criterion-cell stability, write margin, read speed and leakage into a single metric. This metric …
A 32 nm high-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation
SRAM bitcell design margin continues to shrink due to random and systematic process
variation in scaled technologies and conventional SRAM faces a challenge in realizing the …
variation in scaled technologies and conventional SRAM faces a challenge in realizing the …
A comprehensive and critical re-assessment of 2-stage energy level NBTI model
The two stage aka four energy level NBTI model has been comprehensively re-evaluated by
investigating its predictive capabilities beyond the ultra-short stress duration for which it was …
investigating its predictive capabilities beyond the ultra-short stress duration for which it was …
An SRAM Reliability Test Macro for Fully Automated Statistical Measurements of Degradation
Negative bias temperature instability (NBTI) has been considered as a main reliability issue
in SRAMs since the threshold voltage degradation of PMOS transistors due to NBTI has …
in SRAMs since the threshold voltage degradation of PMOS transistors due to NBTI has …