Sparseloop: An analytical approach to sparse tensor accelerator modeling
In recent years, many accelerators have been proposed to efficiently process sparse tensor
algebra applications (eg, sparse neural networks). However, these proposals are single …
algebra applications (eg, sparse neural networks). However, these proposals are single …
[图书][B] Electronic design automation: synthesis, verification, and test
This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI
practitioners and researchers in need of fluency in an" adjacent" field will find this an …
practitioners and researchers in need of fluency in an" adjacent" field will find this an …
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity
The existing work on via allocation in 3D ICs ignores power/ground vias' ability to
simultaneously reduce voltage bounce and remove heat. This article develops the first in …
simultaneously reduce voltage bounce and remove heat. This article develops the first in …
Application of deep learning in back-end simulation: Challenges and opportunities
Y Chen, H Pei, X Dong, Z Jin… - 2022 27th Asia and South …, 2022 - ieeexplore.ieee.org
Relentless semiconductor scaling and ever increasing device integration have resulted in
the exponentially growing size of the back-end design, which makes back-end simulation …
the exponentially growing size of the back-end design, which makes back-end simulation …
A multigrid-like technique for power grid analysis
Modern submicron very large scale integration designs include huge power grids that are
required to distribute large amounts of current, at increasingly lower voltages. The resulting …
required to distribute large amounts of current, at increasingly lower voltages. The resulting …
Efficient large-scale power grid analysis based on preconditioned Krylov-subspace iterative methods
TH Chen, CCP Chen - Proceedings of the 38th annual Design …, 2001 - dl.acm.org
In this paper, we propose preconditioned Krylov-subspace iterative methods to perform
efficient DC and transient simulations for large-scale linear circuits with an emphasis on …
efficient DC and transient simulations for large-scale linear circuits with an emphasis on …
Impact of power-supply noise on timing in high-frequency microprocessors
M Saint-Laurent, M Swaminathan - IEEE Transactions on …, 2004 - ieeexplore.ieee.org
This paper analyzes the impact of power-supply noise on the performance of high-frequency
microprocessors. First, delay models that take this noise into account are proposed for …
microprocessors. First, delay models that take this noise into account are proposed for …
Power grid analysis using random walks
This paper presents a class of power grid analyzers based on a random-walk technique. A
generic algorithm is first demonstrated for dc analysis, with linear runtime and the desirable …
generic algorithm is first demonstrated for dc analysis, with linear runtime and the desirable …
[图书][B] Advanced model order reduction techniques in VLSI design
Model order reduction (MOR) techniques reduce the complexity of VLSI designs, paving the
way to higher operating speeds and smaller feature sizes. This book presents a systematic …
way to higher operating speeds and smaller feature sizes. This book presents a systematic …
Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning
S Zhao, K Roy, CK Koh - IEEE Transactions on Computer-Aided …, 2002 - ieeexplore.ieee.org
We investigate the problem of decoupling capacitance (decap) allocation for power supply
noise suppression at floorplan level. First, we assume that a floorplan is given and consider …
noise suppression at floorplan level. First, we assume that a floorplan is given and consider …