AES on FPGA from the fastest to the smallest
T Good, M Benaissa - … Hardware and Embedded Systems–CHES 2005 …, 2005 - Springer
Two new FPGA designs for the Advanced Encryption Standard (AES) are presented. The
first is believed to be the fastest, achieving 25 Gbps throughput using a Xilinx Spartan-III …
first is believed to be the fastest, achieving 25 Gbps throughput using a Xilinx Spartan-III …
[图书][B] Reconfigurable computing: Accelerating computation with field-programmable gate arrays
MB Gokhale, PS Graham - 2006 - books.google.com
A one-of-a-kind survey of the field of Reconfigurable Computing Gives a comprehensive
introduction to a discipline that offers a 10X-100X acceleration of algorithms over …
introduction to a discipline that offers a 10X-100X acceleration of algorithms over …
[图书][B] Handbook on securing cyber-physical critical infrastructure
The worldwide reach of the Internet allows malicious cyber criminals to coordinate and
launch attacks on both cyber and cyber-physical infrastructure from anywhere in the world …
launch attacks on both cyber and cyber-physical infrastructure from anywhere in the world …
An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA
A Soltani, S Sharifian - Microprocessors and Microsystems, 2015 - Elsevier
Abstract AES (Advanced Encryption Standard) is one of the most popular symmetric key
encryption algorithms. S-box (Substitution block) is main block in AES. In contrast to many …
encryption algorithms. S-box (Substitution block) is main block in AES. In contrast to many …
Implementation of the AES-128 on Virtex-5 FPGAs
P Bulens, FX Standaert, JJ Quisquater… - … on Cryptology in Africa, 2008 - Springer
This paper presents an updated implementation of the Advanced Encryption Standard (AES)
on the recent Xilinx Virtex-5 FPGAs. We show how a modified slice structure in these …
on the recent Xilinx Virtex-5 FPGAs. We show how a modified slice structure in these …
A new methodology to implement the AES algorithm using partial and dynamic reconfiguration
JM Granado-Criado, MA Vega-Rodríguez… - Integration, 2010 - Elsevier
Wireless networks are very widespread nowadays, so secure and fast cryptographic
algorithms are needed. The most widely used security technology in wireless computer …
algorithms are needed. The most widely used security technology in wireless computer …
Very small FPGA application-specific instruction processor for AES
T Good, M Benaissa - … Transactions on Circuits and Systems I …, 2006 - ieeexplore.ieee.org
This paper presents two low-area designs for the advanced encryption standard on field-
programmable gate arrays (FPGAs). Both these designs are believed to be the smallest to …
programmable gate arrays (FPGAs). Both these designs are believed to be the smallest to …
Легковесная криптография. Часть 1
АЕ Жуков - Вопросы кибербезопасности, 2015 - cyberleninka.ru
Статья посвящена обзору алгоритмов малоресурсной (легковесной) криптографии,
стойкость которых снижается незначительно, в отличие от объема требуемых …
стойкость которых снижается незначительно, в отличие от объема требуемых …
Design and FPGA implementation of a wireless hyperchaotic communication system for secure real-time image transmission
In this paper, we propose and demonstrate experimentally a new wireless digital encryption
hyperchaotic communication system based on radio frequency (RF) communication …
hyperchaotic communication system based on radio frequency (RF) communication …
High-speed AES encryptor with efficient merging techniques
I Hammad, K El-Sankary… - IEEE Embedded Systems …, 2010 - ieeexplore.ieee.org
This letter presents a new efficient architecture for high-speed advanced encryption
standard (AES) encryptor. This technique is implemented using composite field arithmetic …
standard (AES) encryptor. This technique is implemented using composite field arithmetic …