Verification is one of the central tasks in circuit and system design. Since the components
are used in several safety critical applications, functional correctness has to be ensured. But …

5,497,342 A 3/1996 Mou et al................... 364/786 A parallel counter comprises logic for
generating output bits 5,524,082 A 6/1996 Horstmann et al.......... 364/489 as Symmetrical …

This article presents a brief survey of digital delay fault testing, which lists 100+ references
on fault models, simulators, ATPG, DFT, and tools. Continuing studies are needed in this …

Abstract Quantum-dot Cellular Automata (QCA) has emerged as one of the alternative
technologies for current CMOS technology. It has the advantage of computing at a faster …

A multiplication logic circuit comprises array generation logic and array reduction logic. The
array reduction logic comprises array reduction logic for a first level of array reduction which …

A digital circuit including a Booth encoder having inputs for receiving a plurality of adjacent
bits of a first binary input number, and an encoder control input for allowing selection …

Design methods for OR-AND-OR three-level networks are useful for exploiting the flexibility
of logic blocks in many complex programmable logic devices. This paper presents T RIMIN …

Traditional scan based transition delay fault tests can potentially miss variability induced
delay faults on long interconnects. On the other hand, an ATPG may not be successful in …

(57) ABSTRACT A parallel counter comprises logic for generating output bits as Symmetrical
functions of the input bits. The parallel counter can be used in a multiplication circuit. A …

Sum bit generation circuit includes first logic generating first signal as XOR of first and
second input signals and second signal as the inverse of XOR of the first and second input …