Comparative analysis of adiabatic logic challenges for low power CMOS circuit designs

D Kumar, M Kumar - Microprocessors and Microsystems, 2018 - Elsevier
In a deep sub-micrometer regime as the scaling improves (reduction in feature size), gate
oxide becomes thin and threshold voltage gets reduced, and thus the contribution in power …

Power comparison of CMOS and adiabatic full adder circuit

SG Reddy - arXiv preprint arXiv:1110.1549, 2011 - arxiv.org
Full adders are important components in applications such as digital signal processors
(DSP) architectures and microprocessors. Apart from the basic addition adders also used in …

4× 4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR

N Anuar, Y Takahashi, T Sekine - … on VLSI and System-on-Chip, 2010 - ieeexplore.ieee.org
This paper presents the simulation results of a 4× 4-bit array two phase clocked adiabatic
static CMOS logic (2PASCL) multiplier using 0.18 μm standard CMOS technology. We also …

A novel power efficient 0.64-GFlops fused 32-bit reversible floating point arithmetic unit architecture for digital signal processing applications

AV AnanthaLakshmi, GF Sudha - Microprocessors and Microsystems, 2017 - Elsevier
Floating point digital signal processing technology has become the primary method for real
time signal processing in most digital systems presently. However, the challenges in the …

[HTML][HTML] A low power design using FinFET based adiabatic switching principle: Application to 16-Bit arithmetic logic unit

RH Vanlalchaka, R Maity, NP Maity - Ain Shams Engineering Journal, 2023 - Elsevier
This paper presents a novel 16-bit arithmetic logic unit (ALU) design by cascading simple 1-
bit ALUs using metal–oxide-semiconductor field effect transistor (MOSFET) and FinFET …

[HTML][HTML] Design of a reversible single precision floating point subtractor

AV Anantha Lakshmi, GF Sudha - SpringerPlus, 2014 - Springer
In recent years, Reversible logic has emerged as a major area of research due to its ability
to reduce the power dissipation which is the main requirement in the low power digital circuit …

An efficient design and analysis of low power SRAM memory cell for ULTRA applications

K Gavaskar, US Ragupathy - Asian journal of research in social …, 2017 - indianjournals.com
Power consumption is the fundamental design constraint in Very Large Scale Integration
(VLSI) technology with the improvement in transistor counts and clock frequencies. This …

[PDF][PDF] Comparative analysis of conventional CMOS and energy efficient adiabatic logic circuits

G Singh, R Kumar, MK Sharma - International Journal of emerging …, 2013 - Citeseer
In recent years, low power circuit design has been an important issue in System on Chip
(SoC) and VLSI design areas. Adiabatic logics, which dissipate less power than static CMOS …

Theory, synthesis, and application of adiabatic and reversible logic circuits for security applications

M Morrison - 2014 IEEE Computer Society Annual Symposium …, 2014 - ieeexplore.ieee.org
Programmable reversible logic is emerging as a prospective logic design style for
implementation in modern nanotechnology and quantum computing with minimal impact on …

Low power design and analysis of fundamental logics using adiabatic array logic

TB Singha, S Konwar, S Roy - 2014 International Conference …, 2014 - ieeexplore.ieee.org
With the advent of adiabatic logic, the MOS-based digital circuit design has shown
improvement by leaps and bounds in terms of reducing power. In the same quest, an …