A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most
powerful indicator to compare and to normalize performance of different PLL designs …

A novel phase-noise-filtering technique based on phase-domain averaging is proposed to
suppress the large injection spurs and poor high-frequency phase noise of inductor-less …

Abstract This paper presents a 5.7–6.0 GHz Phase-Locked Loop (PLL) design using a 130
nm 2P6M CMOS process. We propose to suppress reference spur through reducing the …

A CMOS phase noise filter (PNF) enabled by the passive delay line (DL) and phase
detector/charge pump (PD/CP) based frequency discriminator is proposed. The delay …

This paper presents a CMOS DSRC transmitter architecture for China electronic toll
collection systems. A digitally configurable transmitter architecture is proposed to reduce …

Phase-locked loops (PLLs) are widely deployed in most electronic systems to generate a
desired clock frequency, perform clock data recovery (CDR), and achieve frequency or …

The fractional spurs of All Digital Phase-lock Loops (ADPLL) is limited by the resolution and
linearity of the time-to-digital converter (TDC). Although a high resolution narrow range TDC …

Clock multipliers are among the most critical elements in high speed digital circuits. Power
consumption, area, jitter and wide tuning range are key design metrics in these circuits. To …

This letter presents a time-amplifier (TA) enhanced phase noise filter (TAPNF). The PN
improvement strategy and resettable low noise TA design are presented. The 10-GHz …

This paper proposes a low sub-gigahertz frequency generator with fine frequency resolution.
An injection-locked ring oscillator (ILRO) is firstly adopted to obtain multiphase output at …