Demonstration of a nanosheet FET with high thermal conductivity material as buried oxide: Mitigation of self-heating effect
Self-heating-induced thermal degradation is a severe issue in nonplanar MOS architectures.
Especially in stacked gate-all-around (GAA) nanosheet FET (NSFET), the self-heating effect …
Especially in stacked gate-all-around (GAA) nanosheet FET (NSFET), the self-heating effect …
Investigation of self-heating effect in tree-FETs by interbridging stacked nanosheets: a reliability perspective
S Srivastava, M Shashidhara… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
This work comprehensively investigates the self-heating effects (SHEs) in Tree-FET at 5nm
technological nodes. A comparative analysis of Tree-FET with Nanosheet FET (NSFET) …
technological nodes. A comparative analysis of Tree-FET with Nanosheet FET (NSFET) …
Investigation of Analog/RF and linearity performance with self-heating effect in nanosheet FET
In vertically stacked gate-all-around Nanosheet FET (NSFET), the channels/sheets are
wrapped by a low thermal conductivity material, which hinders the active heat flow path and …
wrapped by a low thermal conductivity material, which hinders the active heat flow path and …
Performance evaluation of high-κ dielectric ferro-spacer engineered Si/SiGe hetero-junction line TFETs: a TCAD approach
S Panwar, S Srivastava… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
In this work, we have investigated the impact of ferroelectricity of high-spacers on the
electrical performance of line-tunnel field-effect transistors (L-TFETs) by numerical …
electrical performance of line-tunnel field-effect transistors (L-TFETs) by numerical …
Influences of source/drain extension region on thermal behavior of stacked nanosheet FET
A well-calibrated numerical-simulation-based study reveals that an elongated extension
region can be a notable approach for the self-heating mitigation of nanosheet FETs. It is …
region can be a notable approach for the self-heating mitigation of nanosheet FETs. It is …
Performance optimization of epitaxial-layer based Si/SiGe hetero-junction area scaled tunnel FET label-free biosensors considering steric hindrance
Abstract This paper explores Si/SiGe hetero-junction dielectrically modulated area-scaled
tunnel FET (DM-ASTFET) for label-free bio-sensing applications. The proposed sensor can …
tunnel FET (DM-ASTFET) for label-free bio-sensing applications. The proposed sensor can …
Design and performance analysis of Si-SiGe heterostructure based double gate feedback FET
The design and performance analysis of a Si-SiGe heterostructure-based double gate
feedback field-effect transistor (HDG FBFET) are presented in this paper. The proposed …
feedback field-effect transistor (HDG FBFET) are presented in this paper. The proposed …
Performance investigation of source/drain extension region on nanosheet FET: a digital design perspective
An in-depth physics-based investigation of source/drain extension region on Nanosheet FET
(NSFET) is presented in this work. A drain-extended NSFET exhibit∼ 15× decrement in I …
(NSFET) is presented in this work. A drain-extended NSFET exhibit∼ 15× decrement in I …
Understanding the Impact of Extension Region on Stacked Nanosheet FET: Analog Design Perspective
This work incorporates an in-depth physics-based investigation of Nanosheet FET's
(NSFET's) extension region for analog circuit design. When extension length (L EXT) is …
(NSFET's) extension region for analog circuit design. When extension length (L EXT) is …
FS-iTFET: advancing tunnel FET technology with Schottky-inductive source and GAA design
JT Lin, WH Tai - Discover Nano, 2024 - Springer
In this paper, we introduce a novel Forkshape nanosheet Inductive Tunnel Field-Effect
Transistor (FS-iTFET) featuring a Gate-All-Around structure and a full-line tunneling …
Transistor (FS-iTFET) featuring a Gate-All-Around structure and a full-line tunneling …