This thesis explores the design and architecture of a balanced ternary RISC-V-like Energy
efficient Balanced tErnary Logic (REBEL)-2 Central Processing Unit (CPU). There is a …

Ternary logic theory and CNTFETs The basic theory of ternary logic and CNTFETs are
explored and explained, to set a theoretical context and build a base for the rest of the …

This thesis presents two circuits capable of writing ternary data to a memristor, and reading
that data without corrupting it. It also investigated how the mean metastable switch memristor …