FPGA-Based Cross-Hardware MBU Emulation Platform for Layout-Level Digital VLSI

X Chen, L Huo, Y Xie, Z Shen, Z Xiang… - 2023 IEEE 32nd …, 2023 - ieeexplore.ieee.org
As the feature size of integrated circuits (ICs) continues to shrink, radiation-induced multiple
bit upsets (MBUs) become more frequent than single bit upsets (SBUs) in nanometer ICs …

Cross-layer fault-space pruning for hardware-assisted fault injection

C Dietrich, A Schmider, O Pusz, GP Vayá… - Proceedings of the 55th …, 2018 - dl.acm.org
With shrinking structure sizes, soft-error mitigation has become a major challenge in the
design and certification of safety-critical embedded systems. Their robustness is quantified …

Spatial and temporal redundancy for transient fault-tolerant datapath

A Sengupta, D Kachave - IEEE Transactions on Aerospace and …, 2017 - ieeexplore.ieee.org
In application specific integrated circuits used in aircraft control systems the effects of
transient fault, both in temporal and spatial domain emanating from a single particle strike …

FLINT+: A runtime-configurable emulation-based stochastic timing analysis framework

M Weißbrich, L Gerlach, H Blume, A Najafi… - Integration, 2019 - Elsevier
Abstract ASICs for Stochastic Computing conditions are designed for higher energy-
efficiency or performance by sacrificing computational accuracy due to intentional circuit …

Radiation Tolerant Reconfigurable Hardware Architecture Design Methodology

E Trumann, GB Thieu, J Schmechel… - … Symposium on Applied …, 2023 - Springer
The purpose of this research topic is to investigate the properties of reconfigurable devices
(ie, FPGA) under a radiation environment to finally propose a new methodology to design …

SEU/SET Evaluation of Digital VLSI Design from Register Transfer Level to Layout Level

X Chen, L Huo, Z Shen, Z Jiang… - 2023 7th International …, 2023 - ieeexplore.ieee.org
As the feature size of integrated circuit (IC) continues to shrink, the soft failure probability
induced by single event upset and single event transient (SEU/SET) for ICs exposing to …

Nocfi: A hybrid fault injection method for networks-on-chip

A Coelho, NE Zergainoh… - 2019 IEEE Latin American …, 2019 - ieeexplore.ieee.org
Networks-On-Chip (NoCs) have emerged as a promising solution to replace global on-chip
interconnections in System-On-Chip (SoC) thanks to better performance and lower power …

KAVUAKA: a low-power application-specific processor architecture for digital hearing aids

L Gerlach - 2021 - repo.uni-hannover.de
The power consumption of digital hearing aids is very restricted due to their small physical
size and the available hardware resources for signal processing are limited. However, there …

Fault Tolerance and Reliability for Partially Connected 3D Networks-on-Chip

AA da Penha Coelho - 2019 - theses.hal.science
Networks-on-Chip (NoC) have emerged as a viable solution for the communication
challenges in highly complex Systems-on-Chip (SoC). The NoC architecture paradigm …

Checkpoint placement for systematic fault-injection campaigns

C Dietrich, TM Thomas, M Mnich - 2023 IEEE/ACM International …, 2023 - ieeexplore.ieee.org
Shrinking hardware structures and decreasing operating voltages lead to an increasing
number of transient hardware faults, which thus become a core problem to consider for …