Design considerations for interleaved ADCs
B Razavi - IEEE Journal of Solid-State Circuits, 2013 - ieeexplore.ieee.org
Interleaving can relax the power-speed tradeoffs of analog-to-digital converters and reduce
their metastability error rate while increasing the input capacitance. This paper quantifies the …
their metastability error rate while increasing the input capacitance. This paper quantifies the …
A 3.1 mW 8b 1.2 GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS
An 8b 1.2 GS/s single-channel Successive Approximation Register (SAR) ADC is
implemented in 32 nm CMOS, achieving 39.3 dB SNDR and a Figure-of-Merit (FoM) of 34 fJ …
implemented in 32 nm CMOS, achieving 39.3 dB SNDR and a Figure-of-Merit (FoM) of 34 fJ …
A 12-bit, 45-MS/s, 3-mW redundant successive-approximation-register analog-to-digital converter with digital calibration
W Liu, P Huang, Y Chiu - IEEE Journal of Solid-State Circuits, 2011 - ieeexplore.ieee.org
This paper presents a sub-radix-2 redundant architecture to improve the performance of
switched-capacitor successive-approximation-register (SAR) analog-to-digital converters …
switched-capacitor successive-approximation-register (SAR) analog-to-digital converters …
A 10 bit 320 MS/s low-cost SAR ADC for IEEE 802.11 ac applications in 20 nm CMOS
This paper presents a low-cost successive approximation register (SAR) analog-to-digital
converter (ADC) for IEEE 802.11 ac applications. In this paper, a binary-scaled …
converter (ADC) for IEEE 802.11 ac applications. In this paper, a binary-scaled …
A resolution-reconfigurable 5-to-10-bit 0.4-to-1 V power scalable SAR ADC for sensor applications
M Yip, AP Chandrakasan - IEEE Journal of Solid-State Circuits, 2013 - ieeexplore.ieee.org
A power-scalable SAR ADC for sensor applications is presented. The ADC features a
reconfigurable 5-to-10-bit DAC whose power scales exponentially with resolution. At low …
reconfigurable 5-to-10-bit DAC whose power scales exponentially with resolution. At low …
A 1.25-GS/s 7-b SAR ADC with 36.4-dB SNDR at 5 GHz using switch-bootstrapping, USPC DAC and triple-tail comparator in 28-nm CMOS
AT Ramkaj, M Strackx, MSJ Steyaert… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
This paper presents a 1.25-GS/s 7-b single-channel successive approximation register
(SAR) analog-to-digital converter (ADC) that achieves a low input frequency SNDR/SFDR of …
(SAR) analog-to-digital converter (ADC) that achieves a low input frequency SNDR/SFDR of …
[图书][B] CMOS: front-end electronics for radiation sensors
A Rivetti - 2018 - books.google.com
CMOS: Front-End Electronics for Radiation Sensors offers a comprehensive introduction to
integrated front-end electronics for radiation detectors, focusing on devices that capture …
integrated front-end electronics for radiation detectors, focusing on devices that capture …
A decision-error-tolerant 45 nm CMOS 7b 1 GS/s nonbinary 2b/cycle SAR ADC
A compact decision-error-tolerant 2b/cycle SAR ADC architecture is presented. Two DACs
with different designated functions, SIG-DAC and REF-DAC, are implemented to make the …
with different designated functions, SIG-DAC and REF-DAC, are implemented to make the …
An 8-b 400-MS/s 2-b-per-cycle SAR ADC with resistive DAC
An 8-b 400-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-
digital converter (ADC) is fabricated in 65-nm CMOS. With the implementation of a low …
digital converter (ADC) is fabricated in 65-nm CMOS. With the implementation of a low …
[图书][B] Advanced data converters
G Manganaro - 2011 - books.google.com
Need to get up to speed quickly on the latest advances in high performance data
converters? Want help choosing the best architecture for your application? With everything …
converters? Want help choosing the best architecture for your application? With everything …