An efficient 10GBASE-T ethernet LDPC decoder design with low error floors
Z Zhang, V Anantharam… - IEEE Journal of Solid …, 2010 - ieeexplore.ieee.org
A grouped-parallel low-density parity-check (LDPC) decoder is designed for the (2048,
1723) Reed-Solomon-based LDPC (RS-LDPC) code suitable for 10GBASE-T Ethernet. A …
1723) Reed-Solomon-based LDPC (RS-LDPC) code suitable for 10GBASE-T Ethernet. A …
Low density parity check decoder for regular LDPC codes
KK Gunnam - US Patent 8,359,522, 2013 - Google Patents
613371642 B1 V2002 Yaoilleta' 2003/0081693 A1 5/2003 Raghaven etal. 1 1 g.
2003/0087634 A1 5/2003 Raghaven et a1. 613511832 B1 2/2002 We ' 2003/0112896 A1 …
2003/0087634 A1 5/2003 Raghaven et a1. 613511832 B1 2/2002 We ' 2003/0112896 A1 …
Low density parity check decoder for irregular LDPC codes
KK Gunnam - US Patent 8,418,023, 2013 - Google Patents
US8418023B2 - Low density parity check decoder for irregular LDPC codes - Google Patents
US8418023B2 - Low density parity check decoder for irregular LDPC codes - Google Patents …
US8418023B2 - Low density parity check decoder for irregular LDPC codes - Google Patents …
Power reduction techniques for LDPC decoders
A Darabiha, AC Carusone… - IEEE Journal of Solid …, 2008 - ieeexplore.ieee.org
This paper investigates VLSI architectures for low-density parity-check (LDPC) decoders
amenable to low-voltage and low-power operation. First, a highly-parallel decoder …
amenable to low-voltage and low-power operation. First, a highly-parallel decoder …
Design of LDPC decoders for improved low error rate performance: quantization and algorithm choices
Many classes of high-performance low-density parity-check (LDPC) codes are based on
parity check matrices composed of permutation submatrices. We describe the design of a …
parity check matrices composed of permutation submatrices. We describe the design of a …
Area-efficient min-sum decoder design for high-rate quasi-cyclic low-density parity-check codes in magnetic recording
H Zhong, W Xu, N Xie, T Zhang - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
We report a silicon area efficient method for designing a quasi-cyclic (QC) low-density parity-
check (LDPC) code decoder. Our design method is geared to magnetic recording that …
check (LDPC) code decoder. Our design method is geared to magnetic recording that …
A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS
A Darabiha, AC Carusone… - 2007 IEEE Custom …, 2007 - ieeexplore.ieee.org
A bit-serial architecture for multi-Gbps LDPC decoding is demonstrated to alleviate the
routing congestion which is the main limitation for LDPC decoders. We report on a 3.3-Gbps …
routing congestion which is the main limitation for LDPC decoders. We report on a 3.3-Gbps …
RF Chipset for Impulse UWB Radar Using 0.13- InP-HEMT Technology
Y Kawano, Y Nakasha, K Yokoo… - IEEE transactions on …, 2006 - ieeexplore.ieee.org
A novel ultra-wideband impulse radar architecture for 24-GHz-band short-range radar was
developed using 0.13-mum InP high electron-mobility technology. The transmitter part …
developed using 0.13-mum InP high electron-mobility technology. The transmitter part …
Low density parity check decoder
KK Gunnam - US Patent 9,112,530, 2015 - Google Patents
A method and system for decoding low density parity check (“LDPC”) codes. An LDPC
decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic …
decoder includes an R select unit, a Q message first-in first-out (“FIFO”) memory, and a cyclic …
Low density parity check decoder for irregular LDPC codes
KK Gunnam - US Patent 8,555,140, 2013 - Google Patents
(57) ABSTRACT A method and system for decoding low density parity check (“LDPC) codes.
An LDPC decoder includes a control unit that controls decoder processing, the control unit …
An LDPC decoder includes a control unit that controls decoder processing, the control unit …