An overview of systolic arrays for forward and inverse discrete sine transforms and their exploitation in view of an improved approach

DF Chiper, A Cracan, VD Andries - Electronics, 2022 - mdpi.com
This paper aims to present a unified overview of the main Very Large-Scale Integration
(VLSI) implementation solutions of forward and inverse discrete sine transforms using …

Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity

C Duan, J Yang, Y Wang, Y Wang, Y Qi, X He… - Proceedings of the 61st …, 2024 - dl.acm.org
Bit-level sparsity in neural network models harbors immense untapped potential. Eliminating
redundant calculations of randomly distributed zero-bits significantly boosts computational …

[PDF][PDF] Effective lossy and lossless color image compression with Multilayer Perceptron

PL Chithra, AC Tamilmathi - International Journal of Engineering & …, 2018 - academia.edu
This paper presents the effective lossy and lossless color image compression algorithm with
Multilayer perceptron. The parallel structure of neural network and the concept of image …

[PDF][PDF] FPGA implementation of CSD based NN image compression architecture

M Kiran, K Nikhileswar, K Ramanaiah - ICTACT J. Microelectron., 2021 - ictactjournals.in
Complexity will be the critical issue in Very Large Scale Integration (VLSI) implementation of
Image Compression Architectures. Especially it will be predominant issue while dealing with …

信息处理设备和信息处理方法

中村章 - 2019 - Google Patents
CN110574024A - 信息处理设备和信息处理方法- Google Patents CN110574024A - 信息处理
设备和信息处理方法- Google Patents 信息处理设备和信息处理方法 Download PDF Info …

Approximated Canonical Signed Digit for Error Resilient Intelligent Computation

GC Cardarilli, L Di Nunzio, R Fazzolari… - 2019 53rd Asilomar …, 2019 - ieeexplore.ieee.org
Lowering the energy consumption in applications operating on large datasets is one of the
main challenges in modern computing. In this context, it is especially important to lower the …

Information processing device and information processing method

T Hiroi, M Yamamoto, A Nakamura - US Patent 11,030,524, 2021 - Google Patents
There is provided an information processing device to reduce a processing load associated
with inner product operations while also guaranteeing the quantization granularity of weight …