Reliable hardware architectures for cryptographic block ciphers LED and HIGHT

S Subramanian, M Mozaffari-Kermani… - … on Computer-Aided …, 2017 - ieeexplore.ieee.org
Cryptographic architectures provide different security properties to sensitive usage models.
However, unless reliability of architectures is guaranteed, such security properties can be …

Self-repairing adder using fault localization

MA Akbar, JA Lee - Microelectronics Reliability, 2014 - Elsevier
In this paper we propose an area-efficient self-repairing adder that can repair multiple faults
and identify the particular faulty full adder. Fault detection and recovery has been carried out …

Lightweight architectures for reliable and fault detection Simon and Speck cryptographic algorithms on FPGA

P Ahir, M Mozaffari-Kermani… - ACM Transactions on …, 2017 - dl.acm.org
The widespread use of sensitive and constrained applications necessitates lightweight (low-
power and low-area) algorithms developed for constrained nano-devices. However, nearly …

[HTML][HTML] Real-time fault tolerant full adder design for critical applications

P Kumar, RK Sharma - … science and technology, an international journal, 2016 - Elsevier
In the complex computing system, processing units are dealing with devices of smaller size,
which are sensitive to the transient faults. A transient fault occurs in a circuit caused by the …

Design of fault tolerant adders: a review

GH Bin Talib, AH El-Maleh, SM Sait - Arabian Journal for Science and …, 2018 - Springer
Arithmetic circuits, especially the adder, are the heart of any computing system that
comprises numerous processing units ranging from small digital systems to supercomputers …

Fault correcting adder design for low power applications

Pritty - Scientific Reports, 2024 - nature.com
Abstract Field Programmable Gate Arrays are extensively used in space, military, and
commercial sectors due to their reprogrammable nature. In high-safety environments …

Reliable Adder Design: A Review

MA Akbar, A Abubakar, A Bermak - Journal of Physics …, 2024 - iopscience.iop.org
With the increasing complexity of system-on-chip designs, the probability of having soft-
errors is increasing sharply. Since, adder is one of the essential elements present in almost …

Reliable low-latency Viterbi algorithm architectures benchmarked on ASIC and FPGA

MM Kermani, V Singh… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
The Viterbi algorithm is commonly applied to a number of sensitive usage models including
decoding convolutional codes used in communications such as satellite communication …

Self-repairing hybrid adder with hot-standby topology using fault-localization

MA Akbar, B Wang, A Bermak - IEEE Access, 2020 - ieeexplore.ieee.org
Effective self-repairing can be achieved if the fault along with its exact location can be
determined. In this paper, a self-repairing hybrid adder is proposed with fault localization. It …

High-speed and energy efficient carry select adder (CSLA) dominated by carry generation logic

M Nam, Y Choi, K Cho - Microelectronics Journal, 2018 - Elsevier
This paper presents a high-speed, energy efficient carry select adder (CSLA) dominated by
carry generation logics. The proposed architecture is composed of three functional stages–a …