Power and Delay Analysis of a CMOS Inverter
NA Badiger, S Iyer, S Gejji - 2023 International Conference on …, 2023 - ieeexplore.ieee.org
The major challenge in designing and synthesizing VLSI circuits is to minimize propagation
delay and Power Dissipation (P d). This depends on the design parameters such as W/L …
delay and Power Dissipation (P d). This depends on the design parameters such as W/L …