Scalable Multi-Stage CMOS OTAs With a Wide CL-Drivability Range Using Low-Frequency Zeros

MA Mohammed, GW Roberts - IEEE Transactions on Circuits …, 2022 - ieeexplore.ieee.org
This work introduces a multi-stage CMOS OTA design technique that allows cascading
identical gain stages (for arbitrarily scalable high DC gain) while driving an ultra-wide range …

Slew-Rate Analysis of Scalable Multi-Stage CMOS Operational Transconductance Amplifiers

MA Mohammed, AS Emara… - 2024 IEEE 67th …, 2024 - ieeexplore.ieee.org
This paper presents an in-depth analysis of the Slew-Rate (SR) in scalable multi-stage
CMOS Operational Transconductance Amplifiers (OTAs). These OTAs utilize Low …

A low-cost BIST design supporting offline and online tests

A Menbari, H Jahanirad - Journal of Electronic Testing, 2022 - Springer
Offline and online built-in self-test (BIST) designs are low-cost platforms to test very complex
modern chips. The offline BIST design embeds the test pattern generator (TPG) into the chip …

Design of Hybrid Memory Built in Self Test using Linear Feedback Shift Registers

V Midasala, G Lakshminarayana… - 2022 6th …, 2022 - ieeexplore.ieee.org
Built in self-test (BIS T) modules are essential devices in various application, which includes
microprocessors, microcontroller, multi-core system, and multi-processor systems. The …

A stimulus identification method for high-resolution ADC linearity testing using low-precision ramp signals

J Fu, Z Guan, J Cheng, H Xu, J Ke - IEICE Electronics Express, 2024 - jstage.jst.go.jp
Linearity testing of an analog-to-digital converter (ADC) with automatic test equipment is
expensive and challenging. In this paper, an improved method is proposed for high …

Research on Cosine-Sum Windows with Maximum Side-Lobe Decay for High Precision ADC Spectral Testing

J Fu, Z Yang, J Song, Y Zhan, S Qiao - Electronics, 2022 - mdpi.com
Achieving coherent sampling has always been a major challenge in analog-to-digital
converter (ADC) spectral testing. If the coherent sampling condition cannot be met, leakage …

A random shifting data weighted averaging algorithm for Nyquist-rate DAC

J Yuan, L Wu, UF Chio, Y Wang, Y Wang - IEICE Electronics Express, 2023 - jstage.jst.go.jp
This paper proposes a random shifting data weighted averaging (RSDWA) algorithm where
a bidirectional circular shift register is coworked with a pseudo-random sequencer to form a …

Detection of Catastrophic Faults in 6-Bit R-2R Ladder DAC

FY Mohamed, AS Emara… - 2023 8th International …, 2023 - ieeexplore.ieee.org
This paper studies the problem of finding a high coverage minimum test set for a 6-bit R-2R
ladder Digital-to-Analog Converter (DAC). DAC is a versatile component that is used in …

High-coverage analog IP block test generation methodology using low-cost signal generation and output response analysis

J Gomez, N Xama, A Coyette… - 2023 IEEE European …, 2023 - ieeexplore.ieee.org
Today, testing of AMS circuits needs to improve quality towards ppb test escape levels as
well as decrease the test development time to reduce the IC lead time. A defect-oriented …

Implementation of Power Binning-based Logic BIST Control using Activity Factor

V Mounika, S Mishra - 2022 International Conference on …, 2022 - ieeexplore.ieee.org
Built in self-test (BIST) modules are essential devices in various application, which includes
microprocessors, microcontroller, multi-core system, and multi-processor systems. The …