RF bandpass filter design based on CMOS active inductors

Y Wu, X Ding, M Ismail, H Olsson - IEEE Transactions on …, 2003 - ieeexplore.ieee.org
In this paper, a second-order RF bandpass filter based on active inductor has been
implemented in a 0.35/spl mu/m CMOS process. Issues related to the intrinsic quality factor …

[图书][B] Model and design of bipolar and MOS current-mode logic: CML, ECL and SCL digital circuits

M Alioto, G Palumbo - 2005 - books.google.com
The main focus of this book is to provide the reader with a deep understanding of modeling
and design strategies of Current-Mode digital circuits, as well as to organize in a coherent …

A method to derive an equation for the oscillation frequency of a ring oscillator

S Docking, M Sachdev - … Transactions on Circuits and Systems I …, 2003 - ieeexplore.ieee.org
A new method for deriving an equation for the oscillation frequency of a ring oscillator is
proposed. The method is general enough to be used for a variety of types of delay stages …

[图书][B] Power distribution network design for VLSI

QK Zhu - 2004 - books.google.com
A hands-on troubleshooting guide for VLSI network designers The primary goal in VLSI
(very large scale integration) power network design is to provide enough power lines across …

Edge-based sampler offset correction

AM Fuller, J Poulton - US Patent 8,199,866, 2012 - Google Patents
The following description is presented to enable any per son skilled in the art to make and
use the disclosed embodi ments, and is provided in the context of a particular applica tion …

A divider-less, high speed and wide locking range phase locked loop

HR Erfani-Jazi, N Ghaderi - AEU-International Journal of Electronics and …, 2015 - Elsevier
A high performance, high frequency phase-locked loop (PLL), based on a divider-less
structure is presented in this paper. This PLL includes an open-loop phase frequency …

Burst-mode clock and data recovery in optical multiaccess networks using broad-band PLLs

A Li, J Faucher, DV Plant - IEEE Photonics Technology Letters, 2005 - ieeexplore.ieee.org
Broad-band phase-locked loops (PLLs) are proposed for burst-mode clock and data
recovery in optical multiaccess networks. Design parameters for a charge-pump PLL-based …

PET system synchronization and timing resolution using high-speed data links

RJ Aliaga, JM Monzó, M Spaggiari… - … on Nuclear Science, 2011 - ieeexplore.ieee.org
Current PET systems with fully digital trigger rely on early digitization of detector signals and
the use of digital processors, usually FPGAs, for recognition of valid gamma events on single …

Analysis of a half-rate bang-bang phase-locked-loop

M Ramezani, C Andre, T Salama - IEEE Transactions on …, 2002 - ieeexplore.ieee.org
This brief presents the timing analysis of a half-rate phaselocked loop (PLL) with a bang-
bang phase detector. The lock-in behavior of the PLL is discussed and parameters such as …

PLL performance comparison with application to spread spectrum clock generator design

M Hsieh, J Welch, GE Sobelman - Analog Integrated Circuits and Signal …, 2010 - Springer
This paper presents performance, power and area comparisons of LC vs. Ring VCO-based
PLL designs in order to determine the best option for high-speed spread spectrum clock …