[图书][B] CMOS PLL synthesizers: analysis and design
K Shu, E Sánchez-Sinencio - 2006 - books.google.com
Thanks to the advance of semiconductor and communication technology, the wireless
communication market has been booming in the last two decades. It evolved from simple …
communication market has been booming in the last two decades. It evolved from simple …
8.2 8Mb/s 28Mb/mJ robust true-random-number generator in 65nm CMOS based on differential ring oscillator with feedback resistors
On-chip true random number generators (TRNG) have been gaining attention as an
important component for building secure systems [1]. CMOS TRNGs typically exploit device …
important component for building secure systems [1]. CMOS TRNGs typically exploit device …
A PVT tolerant 0.18 MHz to 600MHz self-calibrated digital PLL in 90nm CMOS process
J Lin, B Haroun, T Foo, JS Wang… - … Solid-State Circuits …, 2004 - ieeexplore.ieee.org
This paper presents a digital PLL with logarithmic time digitizer, digitally-controlled oscillator,
and start-up calibration, which achieves a constant damping factor and fractional loop …
and start-up calibration, which achieves a constant damping factor and fractional loop …
[图书][B] Introduction to VLSI systems: a logic, circuit, and system perspective
MB Lin - 2011 - taylorfrancis.com
With the advance of semiconductors and ubiquitous computing, the use of system-on-a-chip
(SoC) has become an essential technique to reduce product cost. With this progress and …
(SoC) has become an essential technique to reduce product cost. With this progress and …
Design of CMOS adaptive-bandwidth PLL/DLLs: A general approach
A phase-locked loop (PLL) and delay-locked loop (DLL) design with adaptively adjusting
bandwidth enables optimal performance over a wide frequency range and across process …
bandwidth enables optimal performance over a wide frequency range and across process …
A versatile 90-nm CMOS charge-pump PLL for SerDes transmitter clocking
ALS Loke, RK Barnes, TT Wee… - IEEE Journal of solid …, 2006 - ieeexplore.ieee.org
This paper presents a low-jitter charge-pump phase-locked loop (PLL) built in standard 90-
nm CMOS for 1 to 10 Gb/s wireline SerDes transmitter clocking. The PLL employs a …
nm CMOS for 1 to 10 Gb/s wireline SerDes transmitter clocking. The PLL employs a …
A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-/spl mu/m CMOS
A 20-GHz phase-locked loop with 4.9 ps/sub pp//0.65 ps/sub rms/jitter and-113.5 dBc/Hz
phase noise at 10-MHz offset is presented. A half-duty sampled-feedforward loop filter that …
phase noise at 10-MHz offset is presented. A half-duty sampled-feedforward loop filter that …
An 18-mW 1.175–2-GHz frequency synthesizer with constant bandwidth for DVB-T tuners
L Lu, J Chen, L Yuan, H Min… - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
A fully integrated 1.175-2-GHz differentially tuned frequency synthesizer aimed for digital
video broadcasting-terrestrial tuners is implemented in a 0.18-mum CMOS process. To …
video broadcasting-terrestrial tuners is implemented in a 0.18-mum CMOS process. To …
The concept of time-average-frequency and mathematical analysis of flying-adder frequency synthesis architecture
L Xiu - IEEE Circuits and Systems Magazine, 2008 - ieeexplore.ieee.org
Flying-adder frequency synthesis architecture is a novel technique of generating frequency
on chip. Since its invention, it has been utilized in many commercial products to cope with …
on chip. Since its invention, it has been utilized in many commercial products to cope with …
A 0.9–2.25-GHz sub-0.2-mW/GHz compact low-voltage low-power hybrid digital PLL with loop bandwidth-tracking technique
This paper proposes a low-voltage low-power hybrid digital phase-locked loop (LVHDPLL).
It adopts a loop bandwidth-tracking technique to keep the loop bandwidth almost constant in …
It adopts a loop bandwidth-tracking technique to keep the loop bandwidth almost constant in …