Insights into architectural spurs in high performance fractional-N frequency synthesizers
A fractional-N frequency synthesizer inherently exhibits spurs by virtue of the fact that its
output frequency is not an integer multiple of its reference frequency. Until recently, it …
output frequency is not an integer multiple of its reference frequency. Until recently, it …
An adaptive pre-distortion technique to mitigate the DTC nonlinearity in digital PLLs
S Levantino, G Marzin, C Samori - IEEE Journal of Solid-State …, 2014 - ieeexplore.ieee.org
Digital fractional-N phase-locked loops (PLLs) are an attractive alternative to analog PLLs in
the design of frequency synthesizers for wireless applications. However, the main obstacle …
the design of frequency synthesizers for wireless applications. However, the main obstacle …
Benchmark figure of merit extensions for low jitter phase locked loops inspired by new PLL architectures
W Bae - IEEE Access, 2022 - ieeexplore.ieee.org
A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most
powerful indicator to compare and to normalize performance of different PLL designs …
powerful indicator to compare and to normalize performance of different PLL designs …
A calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolation method
A hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase
noise performance of ring oscillator based fractional-N PLLs. The proposed HPC-PI …
noise performance of ring oscillator based fractional-N PLLs. The proposed HPC-PI …
A 1.7 GHz fractional-N frequency synthesizer based on a multiplying delay-locked loop
S Levantino, G Marucci, G Marzin… - IEEE Journal of Solid …, 2015 - ieeexplore.ieee.org
Although multiplying delay-locked loops allow clock frequency multiplication with very low
phase noise and jitter, their application has been so far limited to integer-N multiplication …
phase noise and jitter, their application has been so far limited to integer-N multiplication …
A 2.4-GHz RF Fractional- Synthesizer With BW
A fractional-N synthesizer architecture incorporates a 35-tap finite impulse response filter
that suppresses the ΣA noise, but does not affect the loop bandwidth (BW). Employing a …
that suppresses the ΣA noise, but does not affect the loop bandwidth (BW). Employing a …
Analysis and Mitigation of Excess Phase Noise and Spurs in Digital-to-Time-Converter-Enhanced Fractional- Frequency Synthesizers
X Wang, MP Kennedy - … Transactions on Circuits and Systems I …, 2024 - ieeexplore.ieee.org
Digital-to-time converters (DTC's) used in fractional-phase locked loops (PLL's) aim to zero
the quantization error (QE) introduced by the divider controller in order to recover integer …
the quantization error (QE) introduced by the divider controller in order to recover integer …
A Fractional- PLL With Space–Time Averaging for Quantization Noise Reduction
This article presents a space–time averaging technique that can realize instantaneous
fractional frequency division, and thus, can significantly reduce the quantization error in a …
fractional frequency division, and thus, can significantly reduce the quantization error in a …
A 2.4-GHz 6.4-mW fractional-N inductorless RF synthesizer
A cascaded synthesizer architecture incorporates a digital delay-line-based filter and an
analog noise trap to suppress the quantization noise of the ΣA modulator. Operating with a …
analog noise trap to suppress the quantization noise of the ΣA modulator. Operating with a …
A 2 GHz synthesized fractional-N ADPLL with dual-referenced interpolating TDC
This paper presents a synthesized 2 GHz fractional-N ADPLL with a dual-referenced
interpolating time-to-digital converter (TDC). The proposed TDC measures fractional phase …
interpolating time-to-digital converter (TDC). The proposed TDC measures fractional phase …