A low-power high-speed two-stage dynamic comparator is presented. In this circuit, the
voltage swing of the first stage of the comparator, pre-amplifier stage, is limited to Vdd/2 in …

A low-power high-speed two-stage dynamic comparator is presented. In this circuit, PMOS
transistors are used at the input of the first and second stages of the comparator. At the …

A low‐power technique for high‐resolution comparators is introduced. In this technique, p‐
type metal‐oxide‐semiconductor field‐effect transistors are employed as the input of the …

An analytical method is presented to characterize stepwise adiabatic circuits (SACs). In this
method, the SACs are modeled as a discrete time system. Unlike previous methods, the …

A new low-power switching procedure for stepwise capacitor chargers is presented. In this
procedure, a novel displacement method is utilized to improve the speed by a factor of two …

A low-power high-speed two-stage dynamic comparator is presented. The voltage
fluctuation at the first stage of the comparator (pre-amplifier stage) is limited to Vdd/2 …

A highly energy-efficiency switching procedure for the capacitor-splitting digital-to-analog
converter (DAC) is presented for successive approximation register (SAR) analogue-to …

In double tail comparators, the pre-amplifier amplifies the input differential voltage and when
the output V cm of the pre-amplifier becomes larger than V th of the latch input transistors …

A new structure of Capacitive Digital to Analog Converters (CDAC) for SAR ADCs is
presented. In this structure, a number of capacitors are used in different series configurations …

In this paper, an analysis on the stepwise adiabatic circuits is presented. In this analysis, the
energy consumption of stepwise adiabatic circuits for the case where it is possible to recycle …