A 0.64-pJ/bit 28-Gb/s/pin high-linearity single-ended PAM-4 transmitter with an impedance-matched driver and three-point ZQ calibration for memory interface
A single-ended four-level pulse-amplitude modulation (PAM-4) transmitter (TX) for memory
interfaces achieves high signal integrity by combining an impedance-matched PAM-4 driver …
interfaces achieves high signal integrity by combining an impedance-matched PAM-4 driver …
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking
YJ Kim, HJ Kwon, SY Doo, M Ahn… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
The graphic DRAM standard GDDR6 is developed to overcome the limitation of previous
standards GDDR5/5X for achieving high-speed operation. This paper introduces 16-Gb …
standards GDDR5/5X for achieving high-speed operation. This paper introduces 16-Gb …
High-Bandwidth and Energy-Efficient Memory Interfaces for the Data-Centric Era: Recent Advances, Design Challenges, and Future Prospects
JH Chae - IEEE Open Journal of the Solid-State Circuits …, 2024 - ieeexplore.ieee.org
Currently, we are living in a data-centric era as the need for large amounts of data has
dramatically increased due to the widespread adoption of artificial intelligence (AI) in a …
dramatically increased due to the widespread adoption of artificial intelligence (AI) in a …
A 20Gb/s dual-mode PAM4/NRZ single-ended transmitter with RLM compensation
C Hyun, H Ko, JH Chae, H Park… - 2019 IEEE International …, 2019 - ieeexplore.ieee.org
In this paper, a 20Gb/s dual-mode four-level pulse amplitude modulation (PAM4)/non-return-
to-zero (NRZ) single-ended voltage-mode transmitter is proposed. Its output drivers are …
to-zero (NRZ) single-ended voltage-mode transmitter is proposed. Its output drivers are …
23.1 a 7.5 Gb/s/pin LPDDR5 SDRAM with WCK clocking and non-target ODT for high speed and with DVFS, internal data copy, and deep-sleep mode for low power
KS Ha, CK Lee, D Lee, D Moon, JH Jang… - … Solid-State Circuits …, 2019 - ieeexplore.ieee.org
High-speed and low-power techniques for the latest mobile DRAMs, such as LPDDR4/4X [1–
3], have been developed to enable high-resolution displays, multiple cameras and 4G …
3], have been developed to enable high-resolution displays, multiple cameras and 4G …
Driving into the memory wall: the role of memory for advanced driver assistance systems and autonomous driving
Autonomous driving is disrupting conventional automotive development. Underlying
reasons include control unit consolidation, the use of components originally developed for …
reasons include control unit consolidation, the use of components originally developed for …
A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free …
High-density and high-speed DRAM requirements have been ever-increasing to achieve a
better user experience for mobile systems, by adopting QHD (2560× 1440), and higher …
better user experience for mobile systems, by adopting QHD (2560× 1440), and higher …
A 15 Gb/s non-return-to-zero transmitter with 1-tap pre-emphasis feed-forward equalizer for low-power ground terminated memory interfaces
This brief presents a 1-tap pre-emphasis transmitter (TX) for a single-ended ground-
terminated memory interface with 28 nm complementary metal-oxide-semiconductor …
terminated memory interface with 28 nm complementary metal-oxide-semiconductor …
A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces
A single-ended transmitter achieves low power consumption with an integrated voltage
modulation (IVM) scheme for memory interfaces. The transmitter preserves the power …
modulation (IVM) scheme for memory interfaces. The transmitter preserves the power …
An analysis on retention error behavior and power consumption of recent DDR4 DRAMs
DM Mathew, M Schultheis… - … , Automation & Test …, 2018 - ieeexplore.ieee.org
DRAM technology is scaling aggressively that results in high leakage power, worse data
retention time behavior, and large process variations. Due to these process variations …
retention time behavior, and large process variations. Due to these process variations …