An all-digital delay-locked loop for 3-D ICs die-to-die clock deskew applications
CC Chung, CY Hou - Microelectronics journal, 2017 - Elsevier
In a system on a chip (SoC), there are several long global wires that typically limit the
maximum SoC clock speed. Therefore, through-silicon via (TSV) technology has been …
maximum SoC clock speed. Therefore, through-silicon via (TSV) technology has been …
Using existing reconfigurable logic in 3D die stacks for test
We propose an architecture for an FPGA-based tester for a 3D stacked IC. Our design
exploits the underlying structure of the FPGA, allowing it to be used to efficiently store and …
exploits the underlying structure of the FPGA, allowing it to be used to efficiently store and …
Using a FPGA in a 3Dd Stacked IC to Prevent LSIB Bitstream Snooping
Y Sun - 2015 - search.proquest.com
The new IEEE Standard, 1687, is intended to enhance the accessibility of embedded
instruments and data. This standard uses data shifted through the scan chain to open …
instruments and data. This standard uses data shifted through the scan chain to open …