An analog fractional-sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms
jitter, integrated from 10 kHz to 10 MHz, and a− 249.7-dB figure of merit (FoM) at the …

This work presents a 6-GHz low-jitter and high figure-of-merit (FoM) fractional-phase-locked
loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture. To …

A fractional-N frequency synthesizer inherently exhibits spurs by virtue of the fact that its
output frequency is not an integer multiple of its reference frequency. Until recently, it …

This article presents a fractional-N frequency synthesizer architecture that is able to
overcome the limitations of conventional bang-bang phase-locked loops. A digital …

Resistive-random-access-memory (ReRAM) based processing-in-memory (R2PIM)
accelerators show promise in bridging the gap between Internet of Thing devices' …

The mid-rise time-to-digital converter (TDC), eg, a binary (bang-bang) phase detector and
other few-bit TDCs, is commonly used as the phase detector (PD) in a digital phase locked …

A fractional-N sub-sampling PLL architecture based on pipelined phase-interpolator and
Digital-to-Time-Converter (DTC) is presented in this paper. The combination of pipelined …

A digital fractional-N PLL that employs a high resolution TDC and a truly ΔΣ fractional divider
to achieve low in-band noise with a wide bandwidth is presented. The fractional divider …

This paper describes a 23-GHz digital bang-bang phase-locked loop (PLL) fabricated in 65-
nm CMOS for millimeter-wave frequency-modulated continuous-wave radars. The presented …

A digital-to-time converter (DTC) controls time delay by a digital code, which is useful, for
example, in a sampling oscilloscope, fractional-N PLL, or time-interleaved ADC. This paper …