FinFET versus gate-all-around nanowire FET: Performance, scaling, and variability
Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around
(GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two …
(GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two …
Review of advanced CMOS technology for post-Moore era
M Li - Science China Physics, Mechanics and Astronomy, 2012 - Springer
The continuous downsizing of device has sustained Moore's law in the past 40 years. As the
power dissipation becomes more and more serious, a lot of emerging technologies have …
power dissipation becomes more and more serious, a lot of emerging technologies have …
[图书][B] Modeling nanowire and double-gate junctionless field-effect transistors
F Jazaeri, JM Sallese - 2018 - books.google.com
The first book on the topic, this is a comprehensive introduction to the modeling and design
of junctionless field effect transistors (FETs). Beginning with a discussion of the advantages …
of junctionless field effect transistors (FETs). Beginning with a discussion of the advantages …
Characterization and analysis of gate-all-around Si nanowire transistors for extreme scaling
The gate-all-around (GAA) silicon nanowire transistor (SNWT) is considered as one of the
best candidates for ultimately scaled CMOS devices at the end of the technology roadmap …
best candidates for ultimately scaled CMOS devices at the end of the technology roadmap …
Impact of process variation on nanosheet gate-all-around complementary FET (CFET)
X Yang, X Li, Z Liu, Y Sun, Y Liu, X Li… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
In this work, dc characteristic variations of nanosheet (NS) gate-all-around (GAA)
complementary FET (CFET) induced by process fluctuations are investigated for the first …
complementary FET (CFET) induced by process fluctuations are investigated for the first …
Design study of gate-all-around vertically stacked nanosheet FETs for sub-7nm nodes
Vertically stacked horizontal nanosheet gate-all-around transistors seem to be one of the
viable solutions toward scaling down below sub-7nm technology nodes. In this work, we …
viable solutions toward scaling down below sub-7nm technology nodes. In this work, we …
Investigations on line-edge roughness (LER) and line-width roughness (LWR) in nanoscale CMOS technology: Part II–experimental results and impacts on device …
In the part I of this paper, the correlation between line-edge roughness (LER) and line-width
roughness (LWR) is investigated by theoretical modeling and simulation. In this paper …
roughness (LWR) is investigated by theoretical modeling and simulation. In this paper …
Impact of fin line edge roughness and metal gate granularity on variability of 10-nm node SOI n-FinFET
A Sudarsanan, S Venkateswarlu… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
We report the numerical simulation study on the characteristic variability of 10-nm SOI Multi
Fin n-FET due to the impact of random fluctuation sources such as gate work function …
Fin n-FET due to the impact of random fluctuation sources such as gate work function …
Extraction of process variation parameters in FinFET technology based on compact modeling and characterization
A parameter extraction methodology of statistical process variations in FinFET is presented
in this paper. First, the main impacts of various variation sources are decomposed, with …
in this paper. First, the main impacts of various variation sources are decomposed, with …
Impact of equivalent oxide thickness on threshold voltage variation induced by work-function variation in multigate devices
Y Lee, C Shin - IEEE Transactions on Electron Devices, 2017 - ieeexplore.ieee.org
Using 3-D technology computer aided design simulation, we investigated the impact of
equivalent oxide thickness (EOT) on threshold voltage (VTH) variation induced by work …
equivalent oxide thickness (EOT) on threshold voltage (VTH) variation induced by work …