The current status of VLSI layout and directions for future research are addressed, with
emphasis on the authors' own work. Necessary terminology and definitions and, whenever …

Wirelength estimation in VLSI layout is fundamental to any pre-detailed routing estimate of
timing or routability. In this paper, we develop new wirelength estimation techniques …

The algorithms and the implementation of a novel macro/custom cell chip-planning,
placement, and global routing package are presented. The simulated-annealing-based …

The complexity of circuit designs has necessitated a top-down approach to layout synthesis.
A large body of work shows that a good layout hierarchy, or partitioning tree, as measured …

Interconnect prediction is very important for early feasibility studies in modern design flows.
Most of the interconnect estimation techniques estimate average or total wirelength and …

The unlimited growth in internet and multimedia leads to large usage of images resulting in
huge storage and distribution of multimedia contents. With increasing use of digital …

FPGA's combine the logic integration benefits of custom VLSI with the design, production,
and time-to-market advantages of standard logic IC's. The Actel family of FPGA's exemplifies …

In this paper, we present an accurate model for prediction of physical desi n characteristics,
such as interconnection lengths anf layout areas, for standard cell layouts. This model …

Interconnect planning is becoming an important design issue for large field programmable
gate array (FPGA)-based designs. One of the most important issues for planning …

This paper studies the prediction of interconnect delay in an industrial setting. Industrial
circuits and two industrial field-programmable gate-array (FPGA) architectures were used in …