A design of power-efficient AES algorithm on Artix-7 FPGA for green communication
K Kumar, A Kaur, KR Ramkumar… - 2021 International …, 2021 - ieeexplore.ieee.org
With the development and growth in industries, the society and the environment are facing
two huge problems. Advancement in technology have raised the problem of communication …
two huge problems. Advancement in technology have raised the problem of communication …
Effect of different nano meter technology based FPGA on energy efficient UART design
In this paper, the main aim of authors is to design UART that is implemented on Xilinx ISE
Design 14.1 and results were tested on Virtex-4 90nm FPGA, Virtex-5 65nm FPGA and …
Design 14.1 and results were tested on Virtex-4 90nm FPGA, Virtex-5 65nm FPGA and …
Scaling of output load in energy efficient FIR filter for green communication on ultra-scale FPGA
FIR Filter always remains in linear phase with the help of symmetric coefficient. This feature
makes it ideal for phase-sensitive applications like data communications. Design of FIR filter …
makes it ideal for phase-sensitive applications like data communications. Design of FIR filter …
GaAs-Based Serial-Input-Parallel-Output Interfaces for Microwave Core-Chips
Microwave core-chips are highly integrated MMICs that are in charge of all the beam-
shaping functions of a transmit-receive module within a phased array system. Such chips …
shaping functions of a transmit-receive module within a phased array system. Such chips …
Reconfigured VLSI architecture for discrete wavelet transform
This paper presents reconfigured dual-memory controller-based VLSI architecture for
discrete wavelet transform to meet the wide variety of diverse computing requirements of the …
discrete wavelet transform to meet the wide variety of diverse computing requirements of the …
Role of scaling of frequency and toggle rate in POD IO standards based energy efficient ALU design on ultra scale FPGA
In this work, we are using frequency scaling, toggle rate scaling and of POD IO standard to
design and implement energy efficient 64-bit ALU on ultra scale FPGA. We have analyzed …
design and implement energy efficient 64-bit ALU on ultra scale FPGA. We have analyzed …
Analysis of nonlinear power distribution network and estimation of jitter transfer functions based on output buffer pseudo open drain termination
Y Liu, Y Yan, X Chu, Y Li - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
With increasing data rates of links, jitter budget allowable for the channel keeps decreasing,
and precisely estimating jitter becomes very important to have confidence in designing a …
and precisely estimating jitter becomes very important to have confidence in designing a …
[PDF][PDF] Low Power Digital Clock Design Using LVCMOS Input/Output Standards on 45nm FPGA
This is an approach to design an efficient digital clock that consumes low amount of power.
This is done by varying frequency to different levels and checking corresponding amount of …
This is done by varying frequency to different levels and checking corresponding amount of …
Power Efficient Arithmetic and Logical Unit Design on FPGA
Arithmetic Logic Unit (ALU) is one of the most crucial part of all the digital circuits that is used
to perform arithmetic and logical operations. An energy and power efficient ALU is designed …
to perform arithmetic and logical operations. An energy and power efficient ALU is designed …
[PDF][PDF] 28nm FPGA based power optimized UART design using HSTL I/O standards
UART abbreviated as Universal Asynchronous Receiver Transmitter is one of the essential
element of communication system. It is being mostly used when there is a short-distance …
element of communication system. It is being mostly used when there is a short-distance …