Integrated circuit having memory array including ECC and column redundancy and method of operating same
AP Singh - US Patent 8,402,326, 2013 - Google Patents
An integrated circuit device comprising a memory cell array having a plurality of memory
cells arranged in a matrix of rows and columns; multiplexer circuitry, coupled to the memory …
cells arranged in a matrix of rows and columns; multiplexer circuitry, coupled to the memory …
Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same
P Bauser - US Patent 7,957,206, 2011 - Google Patents
(*) Notice: Subject to any disclaimer, the term of this “Memory Design Using a One-Transistor
GainCell on SOI, IEEE patent is extended or adjusted under 35 J 1 of Soli ournal of Solid …
GainCell on SOI, IEEE patent is extended or adjusted under 35 J 1 of Soli ournal of Solid …
Single transistor memory cell
S Okhonin, M Nagoga - US Patent 8,014,195, 2011 - Google Patents
US PATENT DOCUMENTS 3.439, 214. A 4, 1969 Kabell 3,997,799 A 12, 1976 Baker
4,032.947 A 6, 1977 Kesel et al. 4,250,569 A 2, 1981 Sasaki et al. 4,262,340 A 4, 1981 …
4,032.947 A 6, 1977 Kesel et al. 4,250,569 A 2, 1981 Sasaki et al. 4,262,340 A 4, 1981 …
Techniques for reducing a voltage swing
P Wang, E Carman - US Patent 7,933,140, 2011 - Google Patents
Techniques for reducing a voltage swing are disclosed. In one particular exemplary
embodiment, the techniques may be realized as an apparatus for reducing a voltage swing …
embodiment, the techniques may be realized as an apparatus for reducing a voltage swing …
Techniques for providing a semiconductor memory device
SR Banna, MA Van Buskirk, T Thurgate - US Patent 8,547,738, 2013 - Google Patents
5,144,390 5,164,805 5,258,635 5,313.432 5,315,541 5,350,938 5,355.330 5,388,068
5,397,726 5.432, 730 5,446.299 5.448, 513 5,466,625 5,489,792 5,506.436 5,515,383 …
5,397,726 5.432, 730 5,446.299 5.448, 513 5,466,625 5,489,792 5,506.436 5,515,383 …
Techniques for simultaneously driving a plurality of source lines
E Carman - US Patent 7,924,630, 2011 - Google Patents
Techniques for simultaneously driving a plurality of Source lines are disclosed. In one
particular exemplary embodiment, the techniques may be realized as an apparatus for …
particular exemplary embodiment, the techniques may be realized as an apparatus for …
Integrated circuit having memory array including ECC and column redundancy and method of operating the same
AP Singh - US Patent 8,069,377, 2011 - Google Patents
An integrated circuit device (for example, a logic device or a memory device (such as, a
discrete memory device)), including a memory cell array having a plurality of memory cells …
discrete memory device)), including a memory cell array having a plurality of memory cells …
A three-dimensional DRAM using floating body cell in FDSOI devices
X Liu, A Zia, MR LeRoy, S Raman… - 2012 IEEE 15th …, 2012 - ieeexplore.ieee.org
This paper describes the capacitorless 1-transistor (1T) DRAMs exploits the floating body
(FB) effect of Fully depleted (FD) SOI devices, where the transistor body is used as a charge …
(FB) effect of Fully depleted (FD) SOI devices, where the transistor body is used as a charge …
Simulation of intrinsic bipolar transistor mechanisms for future capacitor-less eDRAM on bulk substrate
R Pulicani, O Goducheau, H Degoirat… - 2010 17th IEEE …, 2010 - ieeexplore.ieee.org
Embedded DRAM technology is undergoing a radical evolution. With size reduction,
capacity shrink seems to be a complex obstacle to overcome. Alternative memory cells have …
capacity shrink seems to be a complex obstacle to overcome. Alternative memory cells have …
Floating body field-effect transistors, and methods of forming floating body field-effect transistors
J Liu, MP Violette, C Mouli, H Kirsch, D Li - US Patent 7,948,008, 2011 - Google Patents
In one embodiment, a floating body field-effect transistor includes a pair of source/drain
regions having a floating body channel region received therebetween. The source/drain …
regions having a floating body channel region received therebetween. The source/drain …