This paper presents core fusion, a reconfigurable chip multiprocessor (CMP) architecture
where groups of fundamentally independent cores can dynamically morph into a larger …

This paper describes the architecture and implementation of the Tahoma Web browsing
system. Key to Tahoma is the browser operating system (BOS), a new trusted software layer …

This paper explores the multi-dimensional design space for chip multiprocessors, exploring
the inter-related variables of core count, pipeline depth, superscalar width, L2 cache size …

This note addresses the problem of local stabilization of linear systems subject to control
amplitude and rate saturation. Considering the actuator represented by a first-order system …

This paper describes how a superscalar in-order processor must be modified to support
Simultaneous Multithreading (SMT) such that time-predictability is preserved for hard real …

This paper introduces a new set of long duration captures of Internet traffic headers. The
capture is being performed on a continuous on-going basis and is approaching a year in …

For mobile intelligent robot applications, an 81.6 GOPS object recognition processor is
implemented. Based on an analysis of the target application, the chip architecture and …

Miss rate curves (MRCs) are a fundamental concept in determining the impact of caches on
an application's performance. In our research, we use MRCs to provision caches for …

Abstract 3D die-stacked chips are emerging as intriguing prospects for the future because of
their ability to reduce on-chip wire delays and power consumption. However, they will likely …

In modern computer systems, long memory latency is one of the main bottlenecks micro-
architects are facing for leveraging the system performance especially for memory-intensive …