A design of power-efficient AES algorithm on Artix-7 FPGA for green communication
K Kumar, A Kaur, KR Ramkumar… - 2021 International …, 2021 - ieeexplore.ieee.org
With the development and growth in industries, the society and the environment are facing
two huge problems. Advancement in technology have raised the problem of communication …
two huge problems. Advancement in technology have raised the problem of communication …
Effect of different nano meter technology based FPGA on energy efficient UART design
In this paper, the main aim of authors is to design UART that is implemented on Xilinx ISE
Design 14.1 and results were tested on Virtex-4 90nm FPGA, Virtex-5 65nm FPGA and …
Design 14.1 and results were tested on Virtex-4 90nm FPGA, Virtex-5 65nm FPGA and …
Pseudo open drain IO standards based energy efficient solar charge sensor design on 20nm FPGA
K Kalia, B Pandey, K Nanda, S Malhotra… - 2015 IEEE 11th …, 2015 - ieeexplore.ieee.org
In this paper an approach is made to design Pseudo open drain IO standards Based Energy
efficient solar charge sensor design on 20nm and 28nm technology. We have used …
efficient solar charge sensor design on 20nm and 28nm technology. We have used …
[PDF][PDF] Energy Efficient CRC Design for Processor of Workstation, and Server using LVCMOS
In our work we have designed CRC using the LVCMOS IO standards which are stands for
Low Voltage Complementary Metal Oxide Semiconductor. In this work we have worked with …
Low Voltage Complementary Metal Oxide Semiconductor. In this work we have worked with …
LVCMOS based green data flip flop design on FPGA
An energy and power efficient Data Flip Flop has been designed on FPGA in the following
paper in order to meet the energy crises across the globe. Two energy and power efficient …
paper in order to meet the energy crises across the globe. Two energy and power efficient …
[PDF][PDF] Capacitance scaling based energy efficient and tera hertz design of malayalam unicode reader on FPGA
Malayalam is Kerala's official language, south-western region of India mainly speak this
language, and very less research has been done for designing Malayalam Unicode reader …
language, and very less research has been done for designing Malayalam Unicode reader …
LVCMOS Based Low Power Implementation of DES Encryption Algorithm on 28nm FPGA
The main objective of Input/Output (IO) standard is to match the impedance of input and
output port along with FPGA device. During our research, we observe that different IO …
output port along with FPGA device. During our research, we observe that different IO …
Implementation and Analysis on FIFO using FPGA
S Shrivastava, A Kaur - 2024 2nd International Conference on …, 2024 - ieeexplore.ieee.org
Several regions across India are currently experiencing significant energy shortages. This
study investigates the implementation of an optimized First-In-First-Out (FIFO) mechanism …
study investigates the implementation of an optimized First-In-First-Out (FIFO) mechanism …
[PDF][PDF] Design SSTL based Arithmetic Logic Unit for Internet of Things Based Processor
C Patel, A Saxena - International Journal of Engineering and …, 2022 - researchgate.net
Now days in area of computer science Green computing is creating revolution by bringing
some new digital component with less power consumption. Our research work is created on …
some new digital component with less power consumption. Our research work is created on …
[PDF][PDF] Thermally aware LVCMOS based low power universal asynchronous receiver transmitter design on FPGA
Green communication is the latest research trend practiced by researcher in green
computing and network communication. There is no extensive work in green UART design …
computing and network communication. There is no extensive work in green UART design …