An integrated circuit device comprising a memory cell array having a plurality of memory
cells arranged in a matrix of rows and columns; multiplexer circuitry, coupled to the memory …

There are many inventions described herein as well as many aspects and embodiments of
those inventions, for example, multi-bit memory cell and circuitry and techniques for reading …

(57) ABSTRACT A data storage device such as a DRAM memory having a plurality of data
storage cells 10 is disclosed. Each data storage cell 10 has a physical parameter which …

(*) Notice: Subject to any disclaimer, the term of this “Memory Design Using a One-Transistor
GainCell on SOI, IEEE patent is extended or adjusted under 35 J 1 of Soli ournal of Solid …

US PATENT DOCUMENTS 3.439, 214. A 4, 1969 Kabell 3,997,799 A 12, 1976 Baker
4,032.947 A 6, 1977 Kesel et al. 4,250,569 A 2, 1981 Sasaki et al. 4,262,340 A 4, 1981 …

(57) ABSTRACT A memory cell comprising an electrically floating body tran sistor including
a source region, a drain region, a body region disposed therebetween, wherein the body …

US6759282B2 - Method and structure for buried circuits and devices - Google Patents
US6759282B2 - Method and structure for buried circuits and devices - Google Patents …

(54) METHOD AND STRUCTURE FOR BURIED 5,646,058 A 7/1997 Taur et a1. CIRCUITS
AND DEVICES 5,654,220 A 8/1997 Leedy 5,656,548 A 8/1997 Zavracky et a1.(75) …

6,466,511 B2 10/2002 Fujita et al. 4,791,610 A 12/1988 Takemae 6.479, 862 B1 1 1/2002
King et al. 4.954, 989 A 9, 1990 Auberton-Herve et al. 6,492.211 B1 12/2002 Divakaruni et …

A semiconductor device, such as a memory device or radiation detector, is disclosed, in
which data storage cells are formed on a substrate 13. Each of the data storage cells …