Design for manufacturability and reliability in extreme-scaling VLSI

B Yu, X Xu, S Roy, Y Lin, J Ou, DZ Pan - Science China Information …, 2016 - Springer
In the last five decades, the number of transistors on a chip has increased exponentially in
accordance with the Moore's law, and the semiconductor industry has followed this law as …

Machine learning in nanometer AMS design-for-reliability

T Chen, Q Sun, B Yu - 2021 IEEE 14th International …, 2021 - ieeexplore.ieee.org
With continued scaling, the susceptibility of nanometer CMOS to reliability issues has
increased significantly in analog/mixed-signal (AMS) circuits. The industrial large-scale AMS …

Concurrent guiding template assignment and redundant via insertion for DSA-MP hybrid lithography

J Ou, B Yu, DZ Pan - Proceedings of the 2016 on International …, 2016 - dl.acm.org
Directed Self-Assembly (DSA) is a very promising emerging lithography for 7nm and
beyond, where a coarse guiding template produced by conventional optical lithography can" …

Avoidance vs. repair: New approaches to increasing electromigration robustness in VLSI routing

S Bigalke, J Lienig - Integration, 2020 - Elsevier
Studies on further IC development mutually predict that the reliability of future integrated
circuits (ICs) will be severely endangered by the occurrence of electromigration (EM). The …

Load-aware redundant via insertion for electromigration avoidance

S Bigalke, J Lienig - Proceedings of the 2016 on International …, 2016 - dl.acm.org
The ongoing shrinking of interconnects in integrated circuits (ICs) induces reliability issues
caused by electromigration (EM), including void-induced failure mechanisms in IC vias. We …

[图书][B] Asynchronous On-chip Networks and Fault-tolerant Techniques

W Song, G Zhang - 2022 - taylorfrancis.com
Asynchronous On-Chip Networks and Fault-Tolerant Techniques is the first comprehensive
study of fault-tolerance and fault-caused deadlock effects in asynchronous on-chip networks …

Electromigration-aware local-via allocation in power/ground TSVs of 3-D ICs

S Wang, MB Tahoori - IEEE Transactions on Very Large Scale …, 2017 - ieeexplore.ieee.org
With increasing temperature and current density, electromigration (EM) becomes a major
interconnect reliability concern for 3-D integrated-circuits (3-D ICs). In 3-D power delivery …

Tackling signal electromigration with learning-based detection and multistage mitigation

W Ye, MB Alawieh, Y Lin, DZ Pan - Proceedings of the 24th Asia and …, 2019 - dl.acm.org
With the continuous scaling of integrated circuit (IC) technologies, electromigration (EM)
prevails as one of the major reliability challenges facing the design of robust circuits. With …

Mcfroute 2.0: A redundant via insertion enhanced concurrent detailed router

X Jia, Y Cai, Q Zhou, B Yu - Proceedings of the 26th edition on Great …, 2016 - dl.acm.org
In modern VLSI design, manufacturing yield and chip performance are seriously affected by
via failure. Redundant via insertion is an effective technique recommended by foundries to …

Redundant via insertion in directed self-assembly lithography

W Chung, S Shim, Y Shin - 2016 Design, Automation & Test in …, 2016 - ieeexplore.ieee.org
In directed self-assembly lithography (DSAL), vias that are located close are clustered and
patterned together. A large and complex cluster, however, is not allowed in this process due …